POWER-ON RESET CIRCUIT

• US 20070001721A1
• Filed: 07/01/2005
• Published: 01/04/2007
• Est. Priority Date: 07/01/2005
• Status: Abandoned Application

• Current Assignee: Aimtron Technology Corp. (Global Mixed-Mode Technology Inc.)
• Original Assignee: Aimtron Technology Corp. (Global Mixed-Mode Technology Inc.)
• Inventors: LEE, Rong-Chin, CHEN, Chi-Yang
• Application Number:
  US11/160,635
• Publication Number:
  US 20070001721A1
• Time in Patent Office: Days
• US Class Current: 327/143
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

A power-on reset circuit has a reset starting circuit, a reset finishing circuit, and a latch circuit. The reset starting circuit generates a reset starting signal in response to a power voltage. When the power voltage reaches a predetermined reset finishing voltage, the reset finishing circuit generates a reset finishing signal. The latch circuit generates a power-on reset signal having a first state and a second state. In response to the reset starting signal, the latch circuit causes the power-on reset signal to transition to the first state. In response to the reset finishing signal, the latch circuit causes the power-on reset signal to transition to the second state.

Claims

1. A power-on reset circuit comprising:

a reset starting circuit for generating a reset starting signal in response to a power voltage;

a reset finishing circuit for generating a reset finishing signal when the power voltage reaches a predetermined reset finishing voltage; and

a latch circuit for generating a power-on reset signal having a first state and a second state, wherein;

in response to the reset starting signal, the latch circuit causes the power-on reset signal to transition to the first state, and

in response to the reset finishing signal, the latch circuit causes the power-on reset signal to transition to the second state.

2. The circuit according to claim 1, wherein:

the first state of the power-on reset signal is substantially equal to a ground potential, and

the second state of the power-on reset signal is substantially equal to the power voltage.

3. The circuit according to claim 1, wherein:

the latch circuit enables the reset finishing circuit in response to the reset starting signal.

4. The circuit according to claim 1, further comprising:

a delay circuit coupled between the latch circuit and the reset finishing circuit for enabling the reset finishing circuit by a delay time after the latch circuit causes the power-on reset signal to transition to the first state.

5. The circuit according to claim 1, wherein:

the reset starting circuit comprises;

a voltage detection unit for generating a detection voltage representative of the power voltage, and

a trigger unit for generating the reset starting signal when triggered by the detection voltage.

6. The circuit according to claim 1, wherein:

the reset finishing circuit comprises;

a voltage detection unit for generating a detection voltage representative of the power voltage,

a reference voltage generation unit for generating a reference voltage in association with the predetermined reset finishing voltage, and

a voltage comparison unit for comparing the detection voltage and the reference voltage such that the voltage comparison unit is triggered to generate the reset finishing signal when the detection voltage reaches the reference voltage.

7. The circuit according to claim 6, wherein:

the reset finishing circuit further comprises;

a switch unit, through which the latch circuit turns on current paths of the voltage detection unit, the reference voltage generation unit, and the voltage comparison unit.

8. A power-on reset circuit for generating a power-on reset signal in response to a power voltage, comprising:

a first circuit for causing the power-on reset signal to transition to a first state when the power voltage reaches a first voltage rising from zero;

a second circuit for generating a predetermined second voltage;

a third circuit for generating a detection voltage representative of the power voltage; and

a fourth circuit for comparing the detection voltage and the second voltage so as to causing the power-on reset signal to transition to a second state when the detection voltage reaches the predetermined second voltage.

9. The circuit according to claim 8, further comprising:

a fifth circuit for setting a delay time such that the second, the third, and the fourth circuits are enabled by the delay time after the power voltage reaches the first voltage.

10. The circuit according to claim 8, wherein:

the first state of the power-on reset signal is substantially equal to a ground potential, and

the second state of the power-on reset signal is substantially equal to the power voltage.