DC-DC converter switching transistor current measurement technique

• US 20070001762A1
• Filed: 06/30/2005
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Schrom, Gerhard, Hazucha, Peter, Karnik, Tanay, De, Vivek
• Granted Patent: US 8,134,548 B2
• Time in Patent Office: Days
• US Class Current: 330/255
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 3/155 using semiconductor devices only

Abstract

A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor'"'"'s conductive channel. The second current is less than and proportional to the first current.

Claims

1. An apparatus, comprising:

a) a switching transistor;

b) a pair of transistors having their conductive channels coupled in series, a drain of one of said pair of transistors coupled to one end of said switching transistor'"'"'s conductive channel, a source of the other of said pair of transistors coupled to the other end of said switching transistor'"'"'s conductive channel; and

,

c) a node between said pair of transistors coupled to an input of an amplifier.

2. The apparatus of claim 1 further comprising a second pair of transistors having their conductive channels coupled in parallel, a node between said second pair of transistors coupled to a reference input of said amplifier.

3. The apparatus of claim 2 wherein a transistor of said first pair of transistors is designed to be matched to a transistor of said second pair of transistors.

4. The apparatus of claim 2 wherein a transistor from said first pair of transistors and a transistor from said second pair of transistors each have their gates coupled to said switching transistor'"'"'s gate, and wherein, a second transistor from said first pair of transistors and a second transistor from said second pair of transistors each have their gates coupled to a fixed voltage node.

5. The apparatus of claim 2 wherein a transistor from said first pair of transistors and a first transistor from said second pair of transistors were designed to impose the same resistance, said resistance greater than the resistance posed by the second transistor of said second pair of transistors.

6. The apparatus of claim 1 wherein said amplifier is a common gate amplifier.

7. The apparatus of claim 1 wherein a node at which one of said pair of transistors is coupled to said switching transistor'"'"'s conductive channel is a fixed voltage node.

8. The apparatus of claim 7 wherein said fixed voltage node is a reference node.

9. The apparatus of claim 7 wherein said fixed voltage node is a supply node.

10. The apparatus of claim 1 wherein a first of said pair of transistors is to provide to a second of said pair of transistors a current that is proportional to the current within said switching transistor'"'"'s conductive channel.

11. The apparatus of claim 10 wherein said input of said amplifier is a measurement leg designed to bias said first of said pair of transistors in a linear mode of operation.

12. The apparatus of claim 11 further comprising a second pair of transistors having their conductive channels coupled in parallel, a node between said second pair of transistors coupled to a reference leg of said amplifier.

13. The apparatus of claim 12 further comprising one of said second pair of transistors having one end of its conductive channel coupled to a fixed voltage node at which one of said pair of transistors is said coupled to an end of said switching transistor'"'"'s conductive channel.

19. The method of claim 1 comprising generating a signal that varies linearly with a difference between said first current and another current that flows through a second switching transistor.

14. A method, comprising:

conducting a first current through a switching transistor; and

,

conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across said switching transistor'"'"'s conductive channel, said second current less than and proportional to said first current.

15. The method of claim 14 further comprising:

setting a gate-to-source voltage of a transistor with a voltage appearing at a node between said pair of transistors.

16. The method of claim 15 further comprising:

generating a current that is proportional to said first current in response to said setting.

17. The method of claim 16 wherein said setting further comprises raising said transistor'"'"'s source voltage with said voltage and lowering said transistor'"'"'s gate voltage with a second voltage, said second voltage appearing between a second pair of transistors, one of said second pair of transistors having its gate voltage vary with said switching transistor'"'"'s gate voltage.

18. The method of claim 17 wherein both of said second pair of transistors are operating in a linear region of operation and at least one of said fist pair of transistors are operating in a linear region of operation.

20. A computing system, comprising:

a) one or more processors having an on-chip DC-DC converter, said on chip DC-DC converter comprising a switching transistor and a current measurement circuit, said current measurement circuit comprising

a pair of transistors having their conductive channels coupled in series, a drain of one of said pair of transistors coupled to one end of said switching transistor'"'"'s conductive channel, a source of the other of said pair of transistors coupled to the other end of said switching transistor'"'"'s conductive channel;

a node between said pair of transistors coupled to a measurement leg of an amplifier;

b) a memory controller coupled to said one or more processors;

c) a graphics processor coupled to said memory controller; and

,

d) an LCD display coupled to said graphics processor.

21. The apparatus of claim 20 further comprising a second pair of transistors having their conductive channels coupled in parallel, a node between said second pair of transistors coupled to a reference leg of said amplifier.

22. The apparatus of claim 21 wherein the transistors of said first pair of transistors and said second pair of transistors are all approximately the same size.

23. The apparatus of claim 21 wherein a transistor from said first pair of transistors and a transistor from said second pair of transistors each have their gates coupled to said switching transistor'"'"'s gate.

24. The apparatus of claim 21 wherein a transistor from said first pair of transistors and a first transistor from said second pair of transistors impose the same resistance, said resistance greater than the resistance posed by the second transistor of said second pair of transistors.

25. The apparatus of claim 20 wherein said amplifier is a common gate amplifier.