Gain adjust for SAR ADC
First Claim
1. A SAR analog-to-digital Converter (ADC) with variable gain having a SAR capacitor array with a plurality of switched capacitors therein with varying weights and a SAR controller for sampling an input voltage thereon in a sampling phase, and redistributing the charge stored thereon in a conversion phase in accordance with a SAR conversion algorithm, comprising:
- a gain adjust register for defining an amount of charge to be added or subtracted from the capacitor array prior to the conversion phase relative to a predetermined amount of; and
a charge control device for varying the amount of charge stored in the array prior to the conversion phase in accordance with the contents of said gain adjust register such that the amount of charge redistributed during the conversion phase is adjusted.
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Abstract
A SAR analog-to-digital Converter (ADC) is disclosed with variable gain having a SAR capacitor array with a plurality of switched capacitors therein with varying weights and a SAR controller for sampling an input voltage thereon in a sampling phase, and redistributing the charge stored thereon in a conversion phase in accordance with a SAR conversion algorithm. A gain adjust register is provided for defining an amount of charge to be added or subtracted from the capacitor array prior to the conversion phase relative to a predetermined amount of charge. A charge control device varies the amount of charge stored in the array prior to the conversion phase in accordance with the contents of the gain adjust register such that the amount of charge redistributed during the conversion phase is adjusted.
36 Citations
17 Claims
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1. A SAR analog-to-digital Converter (ADC) with variable gain having a SAR capacitor array with a plurality of switched capacitors therein with varying weights and a SAR controller for sampling an input voltage thereon in a sampling phase, and redistributing the charge stored thereon in a conversion phase in accordance with a SAR conversion algorithm, comprising:
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a gain adjust register for defining an amount of charge to be added or subtracted from the capacitor array prior to the conversion phase relative to a predetermined amount of; and
a charge control device for varying the amount of charge stored in the array prior to the conversion phase in accordance with the contents of said gain adjust register such that the amount of charge redistributed during the conversion phase is adjusted. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A SAR analog-to-digital Converter (ADC) with variable gain comprising:
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a SAR capacitor array with a plurality of switched capacitors therein with varying weights each having a common plate connected to a common node and a switched plate;
a comparator for comparing the voltage on the common node of the capacitor array with a common reference voltage;
a SAR controller for sampling an input voltage on said capacitor array in a sampling phase, and redistributing the charge stored thereon in a conversion phase by selectively increasing the voltage on select ones of said capacitor array in accordance with a SAR conversion algorithm;
a gain adjust register for defining an amount of charge to be added or subtracted from the capacitor array prior to the conversion phase relative to a predetermined amount of charge; and
a charge control device for varying the amount of charge stored in the array prior to the conversion phase in accordance with the contents of said gain adjust register such that the amount of charge redistributed during the conversion phase is adjusted. - View Dependent Claims (8)
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9. The ADC of Clam 8, wherein said charge control device selectively controls the connection of said switched plate of at least one of said array capacitors to force connection thereof to the common reference voltage during the sampling phase, the gain adjust register defining whether said at least one of said array capacitors is connected to the input voltage or the common reference voltage during the sampling phase, wherein gain is decreased when connected to the common reference voltage.
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10. The ADC of Clam 8, wherein said charge control device controls the connection of said switched plate of select ones of said array capacitors to force connection thereof to the common reference voltage during the sampling phase, the gain adjust register defining whether said select ones of said array capacitors are connected to the input voltage or the common reference voltage during the sampling phase, wherein gain is decreased when connected to the common reference voltage.
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11. The ADC of Clam 8, wherein said charge control device controls the connection of said switched plate of at least one of said array capacitors to force connection thereof to the common reference voltage during the sampling phase, the gain adjust register defining whether said at least one of said array capacitors is connected to the input voltage or the common reference voltage during the sampling phase, wherein gain is decreased when connected to the common reference voltage and, wherein an additional capacitor equal in value to said at least one of said array capacitors is connected with one plate thereof connected to said common node and a switched plate controlled by said charge control device so as to sample the input voltage thereon during the sampling phase and connected to the common mode voltage during the conversion phase.
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12. A method for varying the gain of a SAR analog-to-digital Converter (ADC) having a SAR capacitor array with a plurality of switched capacitors therein with varying weights and a SAR controller for sampling an input voltage thereon in a sampling phase, and redistributing the charge stored thereon in a conversion phase in accordance with a SAR conversion algorithm, comprising the steps of:
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defining in a gain adjust register an amount of charge to be added or subtracted from the capacitor array prior to the conversion phase relative to a predetermined amount of charge; and
varying with a charge control device the amount of charge stored in the array prior to the conversion phase in accordance with the contents of the gain adjust register such that the amount of charge redistributed during the conversion phase is adjusted. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification