Display apparatus, and driving circuit for the same

• US 20070001939A1
• Filed: 09/06/2006
• Published: 01/04/2007
• Est. Priority Date: 01/30/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Hashimoto, Yoshiharu, Yoneyama, Teru
• Granted Patent: US 8,614,656 B2
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Abstract

A drive circuit which outputs an output signal to an output terminal, includes a drive transistor configured to output a gradation current to the output terminal; a single differential amplifier; a resistance element connected with the drive transistor; and a plurality of switches. The plurality of switches are controlled such that a precharge voltage is outputted from the differential amplifier to the output terminal in a first period while blocking off an output from the drive transistor and such that a gradation current is outputted from the drive transistor to the output terminal in a second period after the first period.

Claims

1. A drive circuit which outputs an output signal to an output terminal, comprising:

a drive transistor configured to output a gradation current to said output terminal;

a single differential amplifier;

a resistance element connected with said drive transistor; and

a plurality of switches,

wherein said plurality of switches are controlled such that a precharge voltage is outputted from said differential amplifier to said output terminal in a first period while blocking off an output from said drive transistor and such that a gradation current is outputted from said drive transistor to said output terminal in a second period after said first period.

2. The drive circuit according to claim 1, wherein said differential amplifier has differential input transistors, and polarities of signals to be supplied to said differential input transistors are switched every predetermined period.

3. The drive circuit according to claim 1, wherein a first power supply line connected to said differential amplifier and a second power supply line connected to said resistance element are separated from each other.

4. The drive circuit comprising:

an output terminal;

a differential amplifier configured to output a precharge voltage to said output terminal in response to an input signal in a first period; and

a single drive transistor configured to output a gradation current to said output terminal based on an output from said differential amplifier in response to said input signal in a second period after said first period.

5. The drive circuit according to claim 4, further comprising:

a switch circuit configured to switch supply of first and second signals of said input signal to an inversion input and a non-inversion input in said differential amplifier every predetermined period.

6. The drive circuit according to claim 4, wherein a first power supply line connected with said differential amplifier and a second power supply line connected with said drive transistor are separated.

7. The drive circuit according to claim 4, wherein said input signal supplied to said differential amplifier in said first period is determined based on a part of bits of a display data, and

said input signal supplied to said differential amplifier in said second period is determined based on all of bits of said display data.

8. The drive circuit according to claim 4, further comprising:

a first switch configured to prohibit an operation of said drive transistor in said first period.

9. The drive circuit according to claim 4, further comprising:

a second switch configured to disconnect said drive transistor from said output terminal in said first period.

10. The drive circuit according to claim 4, further comprising:

a first resistance element connected in series with said drive transistor; and

a series circuit of a third switch and a second resistance element, said series circuit being connected in parallel to said first resistance element,

wherein said third switch is controlled based on a resistance value of said first resistance element.

11. A drive method for a display apparatus, comprising:

outputting a precharge voltage from a differential amplifier to an output terminal in response to an input signal in a first period; and

outputting a gradation current from a single drive transistor to said output terminal based on an output from said differential amplifier in response to said input signal in a second period after said first period.

12. The drive method according to claim 11, further comprising:

switching supply of first and second signals of said input signal to an inversion input and a non-inversion input in said differential amplifier every predetermined period.

13. The drive method according to claim 11, wherein powers are supplied to said differential amplifier and said drive transistor through different power supply lines, respectively.

14. The drive method according to claim 11, wherein said input signal supplied to said differential amplifier in said first period is determined based on a part of bits of a display data, and

said input signal supplied to said differential amplifier in said second period is determined based on all of bits of said display data.

15. The drive method according to claim 11, further comprising:

prohibiting an operation of said drive transistor in said first period.

16. The drive method according to claim 11, further comprising:

disconnecting said drive transistor from said output terminal in said first period.

17. The drive method according to claim 11, further comprising:

adjusting a resistance value of a resistance element connected in series with said drive transistor.

18. The drive method according to claim 17, wherein the drive method is carried out by a drive circuit, which comprises a resistance element connected in series with said drive transistor;

and a series circuit of a third switch and a second resistance element, said series circuit being connected in parallel to said resistance element, and

said drive method further comprises controlling said third switch based on a resistance value of said first resistance element.

20. The drive method according to claim 12, wherein said input signal supplied to said differential amplifier in said first period is determined based on a part of bits of a display data, and

said input signal supplied to said differential amplifier in said second period is determined based on all of bits of said display data.

19. A drive circuit comprising:

an output terminal; and

a single drive transistor configured to output a drive current to said output terminal in response to a gate input signal,

wherein one of a first voltage corresponding to a difference from a voltage of said input signal to a voltage of a drain of said drive transistor and a second voltage corresponding to a difference from said drain voltage to said input signal voltage is selected every predetermined period, and the selected voltage is supplied to said drive transistor as a gate input signal.