Liquid crystal display device and fabricating method thereof

• US 20070002249A1
• Filed: 06/21/2006
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Nam, Seung, Kwon, Oh, Yoo, Soon, Cho, Heung, Chang, Youn
• Granted Patent: US 8,411,244 B2
• Time in Patent Office: Days
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes

Abstract

A liquid crystal display device and a fabricating method thereof for simplifying a process are disclosed. In the method of fabricating the liquid crystal display device, a first conductive pattern group including a gate line and a gate electrode, a common line and a common electrode, a pixel electrode and a pad in a multiple conductive layer having a stepwise shape including a transparent conductive layer is formed on a substrate by a first mask process. An insulating film and a semiconductor layer including a plurality of contact holes are formed on the first mask pattern group by a second mask process. A second pattern group including a data line, a source electrode and a drain electrode is formed on the semiconductor layer and the semiconductor layer is patterned, and an active layer is exposed between the source electrode and the drain electrode by a third mask process.

Claims

1. A liquid crystal display device, comprising:

a data line crossing a gate line on a substrate to define a pixel area;

an insulating film between the gate line and the data line;

a thin film transistor connected to the gate line and the data line, the thin film transistor having source, drain and gate electrodes;

a pixel electrode connected to the thin film transistor in the pixel area;

a common electrode provided at the pixel area in parallel to the pixel electrode;

a common line connected to the common electrode; and

a pad connected to at least one of the gate line, the data line and the common line;

wherein a first pattern group having the gate line, the gate electrode, the pixel electrode, the common electrode, the common line, and the pad includes a multiple-layered conductive layer including a transparent conductive layer,

wherein the first pattern group has a step shape.

2. The device of claim 1, wherein the first pattern group has a multiple-layered structure having a substantially opaque conductive layer on the transparent conductive layer.

3. The device of claimed in claim 2, wherein the transparent conductive layer is constantly exposed along an edge of the substantially opaque conductive layer.

4. The device of claim 1, wherein the pad exposes the transparent conductive layer via a contact hole.

5. The device of claim 1, further comprising:

a storage capacitor provided by a pixel connecting line extending from the drain electrode of the thin film transistor and overlapping a portion of the common line with the insulating film therebetween.

6. The device of claim 5, further comprising:

a storage capacitor including an upper storage electrode connected to the pixel electrode and overlapping a portion of the gate line with the insulating film therebetween.

7. The device of claim 6, wherein the pixel connecting line is connected to the pixel electrode via a first contact hole passing through the insulating film, and the upper storage electrode is connected to the pixel electrode via a second contact hole passing through the insulating film.

8. The device of claim 7, further comprising:

a semiconductor pattern overlapped with the pixel connecting line and the upper storage electrode.

9. The device of claim 8, wherein the semiconductor pattern does not exist in the first and second contact holes.

10. The device of claim 1, further comprising:

a storage capacitor including an upper storage electrode connected to the pixel electrode and overlapping a portion of the gate line with the insulating film therebetween.

11. The device of claim 10, wherein the upper storage electrode is connected to the pixel electrode via a contact hole passing through the insulating film.

12. The device of claim 11, further comprising:

a semiconductor pattern overlapped with the upper storage electrode.

13. The device of claim 12, wherein the semiconductor pattern does not exist in the contact hole.

14. The device of claim 1, wherein a channel exposed between the source electrode and the drain electrode is oxidized.

15. The device of claim 1, wherein the data line is connected to the pad via a contact hole passing through the insulating film.

16. The device of claim 1, wherein the thin film transistor includes a semiconductor pattern forming a channel, the semiconductor pattern being overlapped with the data line.

17. A liquid crystal display device, comprising:

a pair of electrodes substantially applying an electric field;

wherein the electrodes have a multiple layer structure including an upper part and a lower part wider than the upper part.

18. The device of claim 17, wherein the upper part is substantially opaque material and the lower part is substantially transparent.

19. A method of fabricating a liquid crystal display device, comprising:

a first mask process of forming a first conductive pattern group including a gate line and a gate electrode, a common line and a common electrode, a pixel electrode and a pad in multiple conductive layers including a transparent conductive layer on a substrate, wherein the first conductive pattern group has a step shape;

a second mask process of forming an insulating film and a semiconductor layer including a plurality of contact holes on the first mask pattern group; and

a third mask process of forming a second pattern group including a data line, a source electrode and a drain electrode and a pixel connecting line extended from the drain electrode on the semiconductor layer, patterning the semiconductor layer, and exposing an active layer between the source electrode and the drain electrode.

20. The method of claim 19, wherein the first pattern group has a multiple-layer structure having transparent and substantially opaque conductive layers.

21. The method of claim 20, wherein the transparent conductive layer is exposed along an edge of the substantially opaque conductive layer.

22. The method of claim 19, wherein the first mask process includes:

forming the transparent conductive layer and a substantially opaque conductive layer on the substrate;

forming a photo-resist pattern on the substantially opaque conductive layer; and

patterning the transparent conductive layer and the substantially opaque conductive layer using the photo-resist pattern as a mask.

23. The method of claim 22, wherein the first mask process further includes:

ashing the photo-resist pattern; and

etching the substantially opaque conductive layer exposed through the ashed photo-resist pattern.

24. The method of claim 19, wherein the pad exposes the transparent conductive layer via a contact hole.

25. The method of claim 19, wherein the third mask process includes:

forming a conductive layer on the semiconductor layer;

forming a photo-resist pattern having a different thickness on the conductive layer;

forming the data line, the source electrode, the drain electrode and the pixel connecting line by patterning a conductive layer using the photo-resist pattern as a mask;

patterning the semiconductor layer using the photo-resist pattern as a mask; and

exposing an active layer of the semiconductor layer.

26. The method of claim 25, wherein the third mask process further includes:

oxidizing a surface of the exposed active layer using a plasma surface process.

27. The method of claim 26, wherein the plasma surface process is performed on the condition that the photo-resist pattern exists.

28. The method of claim 19, further comprising forming a storage capacitor provided by the overlapping of the pixel connecting line with a portion of the common line with the insulating film therebetween.

29. The method of claim 28, wherein the third mask process further includes:

forming an upper storage electrode connected to the pixel electrode, and overlapped with a portion of the gate line with the insulating film therebetween along with the second pattern group.

30. The method of claim 29, wherein the pixel connecting line is connected to the pixel electrode via a first contact hole passing through the insulating film, and the upper storage electrode is connected to the pixel electrode via a second contact hole passing through the insulating film.

31. The method of claim 30, wherein the semiconductor layer is overlapped along the pixel connecting line and the upper storage electrode, and is formed in such a manner to not exist in the first and second contact holes.

32. The method of claim 19, wherein the third mask process further includes:

forming an upper storage electrode connected to the pixel electrode, and overlapped with a portion of the gate line with the insulating film therebetween.

33. The method of claim 32, wherein the upper storage electrode is connected to the pixel electrode via a contact hole passing through the insulating film.

34. The method of claim 33, wherein the semiconductor layer is overlapped along the upper storage electrode, and is formed in such a manner to not exist in the contact hole.

35. The method of claim 19, wherein the data line is connected to the pad via a contact hole passing through the insulating film.

36. The method of claim 35, wherein the semiconductor layer is overlapped along the data line, and is formed in such a manner to not exist in the contact hole.

37. The method of claim 19, wherein the third mask process further includes exposing the transparent conductive layer of the pad through the contact hole.

38. The method of claim 19, wherein the third mask process uses one of a half tone mask and a diffractive exposure mask.