FLASH MEMORY DEVICE FOR REDUCING ERROR OCCURRENCE RATIO IN PROGRAM OPERATION AND METHOD OF CONTROLLING PROGRAM OPERATION THEREOF
First Claim
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1. A flash memory device, comprising:
- a memory cell block including memory cells that share a plurality of groups of bit line pairs;
a plurality of groups of page buffers, wherein each group of page buffers is connected to a respective group of bit line pairs and is arranged to output program data to memory cells connected to part of the bit line pairs of corresponding groups in response to a program control signal; and
a program control unit arranged to consecutively generate the program control signal for each group of page buffers at a predetermined time distance during a program operation, wherein during the program operation, while each of the page buffers of one of the plurality of groups of page buffers outputs the program data to the memory cells connected to any one of a corresponding bit line pair, the page buffers of the remaining groups of page buffers do not output the program data.
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Abstract
A flash memory device and method of controlling a program operation thereof, includes page buffers divided into a predetermined number of groups and a program operation is performed on a group basis.
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Citations
9 Claims
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1. A flash memory device, comprising:
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a memory cell block including memory cells that share a plurality of groups of bit line pairs;
a plurality of groups of page buffers, wherein each group of page buffers is connected to a respective group of bit line pairs and is arranged to output program data to memory cells connected to part of the bit line pairs of corresponding groups in response to a program control signal; and
a program control unit arranged to consecutively generate the program control signal for each group of page buffers at a predetermined time distance during a program operation, wherein during the program operation, while each of the page buffers of one of the plurality of groups of page buffers outputs the program data to the memory cells connected to any one of a corresponding bit line pair, the page buffers of the remaining groups of page buffers do not output the program data. - View Dependent Claims (2, 3, 4, 5)
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6. A method of controlling a program control of a flash memory device, comprising:
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storing first program data in a main latch of each of a plurality of groups of page buffers, wherein each group of page buffers is connected to a respective group of bit line pairs;
outputting an internal program signal in response to a program command;
consecutively generating a program control signal for each group of page buffers at a predetermined time distance in response to the internal program signal;
whenever one of the program control signals is generated, outputting first program data stored in page buffers of any one of the plurality of groups of page buffers to memory cells of a selected page connected to part of bit line pairs of any one of the groups of bit line pairs in response to the generated program control signal; and
while the program control signals are consecutively generated, outputting second program data to cache latches of each of the plurality of groups of page buffers. - View Dependent Claims (7, 8, 9)
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Specification