Non-Volatile Memory with Managed Execution of Cached Data
First Claim
1. A non-volatile memory device having addressable pages of memory cells, comprising:
- a set of data latches for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;
a first-in-first-out queue for ordering incoming memory operations to be executed in the core array, the first-out memory operation being the next memory operation to be executed;
a set of mergeable conditions when two or more memory operations are mergeable into a combined memory operation, the combined memory operation operating on all data associated with the operations being combined;
a queue manager for accepting an incoming memory operation into the queue whenever there are sufficient data latches available for caching the data associated with the incoming memory operation; and
whenever an executing memory operation in the core array is mergeable with one or more queued memory operations, said queue manager terminating the executing memory operation and instead executing the combined memory operation of the mergeable memory operations;
or whenever two or more queued memory operations are mergeable among themselves but not with an executing memory operation in the core array, said queue manager executing the combined queued memory operation of the mergeable memory operations after the executing memory operation in the core array has completed.
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Accused Products
Abstract
Methods and circuitry are present for executing current memory operation while other multiple pending memory operations are queued. Furthermore, when certain conditions are satisfied, some of these memory operations are combinable or mergeable for improved efficiency and other benefits. The management of the multiple memory operations is accomplished by the provision of a memory operation queue controlled by a memory operation queue manager. The memory operation queue manager is preferably implemented as a module in the state machine that controls the execution of a memory operation in the memory array.
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Citations
22 Claims
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1. A non-volatile memory device having addressable pages of memory cells, comprising:
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a set of data latches for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;
a first-in-first-out queue for ordering incoming memory operations to be executed in the core array, the first-out memory operation being the next memory operation to be executed;
a set of mergeable conditions when two or more memory operations are mergeable into a combined memory operation, the combined memory operation operating on all data associated with the operations being combined;
a queue manager for accepting an incoming memory operation into the queue whenever there are sufficient data latches available for caching the data associated with the incoming memory operation; and
whenever an executing memory operation in the core array is mergeable with one or more queued memory operations, said queue manager terminating the executing memory operation and instead executing the combined memory operation of the mergeable memory operations;
orwhenever two or more queued memory operations are mergeable among themselves but not with an executing memory operation in the core array, said queue manager executing the combined queued memory operation of the mergeable memory operations after the executing memory operation in the core array has completed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification