Synchronous memory device with output driver controller

• US 20070002675A1
• Filed: 06/30/2006
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Koo, Cheul
• Granted Patent: US 7,511,546 B2
• Time in Patent Office: Days
• US Class Current: 365/233.100
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A synchronous memory device having an output driver controller, comprises a DLL circuit for receiving an external clock and outputting an internal clock; an output driver for outputting data in synchronism with the internal clock; and an output driver controller for controlling operation of the output driver, wherein the output driver controller makes the output driver active after receiving from the DLL circuit a control signal indicating that the internal clock is locked and is in a stabilized state.

Claims

1. A synchronous memory device having an output driver controller, comprising:

a DLL circuit for receiving an external clock and outputting an internal clock;

an output driver for outputting data in synchronism with the internal clock; and

an output driver controller for controlling operation of the output driver,

wherein the output driver controller makes the output driver active after receiving from the DLL circuit a control signal indicating that the internal clock is locked and is in a stabilized state.

2. The synchronous memory device as set forth in claim 1, wherein the DLL circuit includes a counter for counting the toggling number of the external clock;

and the DLL circuit additionally outputs an enable signal for enabling the output driver controller when the toggling number of the external clock which is counted by the counter exceeds a predetermined number.

3. The synchronous memory device as set forth in claim 2, wherein the predetermined number is a minimum toggling number for ensuring that the output signal of the DLL circuit is stabilized.

4. The synchronous memory device as set forth in claim 1, further comprising:

a reset unit for controlling the output driver controller.

5. The synchronous memory device as set forth in claim 4, wherein the reset unit outputs a reset signal for disabling the output driver controller when the synchronous memory device enters a power-down mode or a self-refresh mode or the DLL circuit is reset.

6. The synchronous memory device as set forth in claim 5, wherein, when the reset signal is released, the output driver controller is enabled after receiving from the DLL circuit a control signal indicating that the internal clock is locked and is in a stabilized state.