Continuous power transfer scheme for two-wire serial link

• US 20070003054A1
• Filed: 06/23/2005
• Published: 01/04/2007
• Est. Priority Date: 06/23/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Bark, Boris, Ransijn, Johannes, Kiss, Peter, Yoder, James
• Granted Patent: US 7,940,921 B2
• Time in Patent Office: Days
• US Class Current: 379/413
• CPC Class Codes: H04M 19/001 Current supply source at the exchanger providing current to substations
• CPC Class Codes: H04M 3/005 Interface circuits for subscriber lines current supply H04M19/00 and subgroups; supervisory, monitoring or testing arrangements H04M3/22 and subgroups; in key telephone systems H04M9/006

Abstract

The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.

Claims

1. A method for transferring power from a system-side circuit to a line-side circuit connected via a two-wire interface, comprising the steps of

receiving, at the system-side circuit, a first signal imposed on the two-wire interface by the line-side circuit;

and

reinforcing the first signal at the system-side circuit;

thereby transferring power from the system-side circuit to the line-side circuit via the two-wire interface.

2. The method of claim 1, wherein the step of reinforcing comprises the steps of:

amplifying the first signal to produce a first amplified signal; and

adding the first amplified signal to the first signal.

3. The method of claim 2, further comprising the steps of:

ceasing the step of reinforcing;

receiving, at the system-side circuit, a second signal imposed on the two-wire interface by the line-side circuit;

amplifying the second signal to produce a second amplified signal; and

adding the second amplified signal to the second signal.

4. The method of claim 3, further comprising the step of

latching the first signal;

and

the step of ceasing the step of reinforcing includes the step of disabling the latching of the first signal.

12. The method of claim 11, wherein the step of switching comprises the step of:

inputting at least a portion of the first signal to the input terminal of the tri-state buffer.

13. The method of claim 12, wherein the steps of receiving, switching, and inputting are performed during a first portion of a frame including the first and second time periods.

14. The method of claim 13, further comprising the step of:

inputting, during a second portion of the frame, a second signal to the input terminal of the tri-state buffer, such that the second signal is passed to the output terminal of the tri-state buffer during the second portion of the frame.

15. The method of claim 14, wherein the steps of inputting the first signal and inputting the second signal to the input terminal of the tri-state buffer comprise the steps of:

inputting the first signal and the second signal to a mode selection switch;

providing a mode selection signal to the mode selection switch that causes the mode selection switch to select and output either the first signal or the second signal to the input terminal of the tri-state buffer.

5. A method for low-ripple transfer of power from a system-side circuit to a line-side circuit connected via a two-wire interface, comprising the steps of

transmitting a forward pulse stream from the system-side circuit to the line-side circuit during a first time period;

rectifying the forward pulse stream in the line-side circuit to produce a first rectified voltage during the first time period;

transmitting a reverse pulse stream from the line-side circuit to the system-side circuit during a second time period;

providing a supplemental pulse stream during the second time period;

rectifying the supplemental pulse stream in the line-side circuit to produce a second rectified voltage during the second time period;

whereby a rectified voltage is produced during both the first and second time periods.

6. The method of claim 6, wherein the step of providing a supplemental pulse stream comprises the steps of

receiving, at the system-side circuit, the reverse pulse stream from the line-side circuit;

reinforcing, at the system-side circuit, the reverse pulse stream to produce the supplemental pulse stream; and

transferring the supplemental pulse stream from the system-side circuit to the line-side circuit.

7. The method of claim 6, further comprising the steps of

latching to each pulse in the reverse pulse stream.

8. A method of interfacing a first circuit with a second circuit having a tri-state buffer connected between a storage device and ground, the tri-state buffer including an input terminal, an enable terminal, and an output terminal, comprising the steps of:

receiving a first signal having an AC-frequency component at the output terminal of the tri-state buffer, and

switching the tri-state buffer, such that (i) during a first time period, the first signal is electrically connected to the storage capacitor, and (ii) during a second time period, the first signal is electrically connected to ground.

9. The method of claim 8, wherein during the first time period the voltage of the first signal is above a first predetermined level;

and wherein during the second time period the voltage of the first signal is below a second predetermined level.

10. The method of claim 9, wherein the first predetermined level is approximately the voltage at the storage device, and the second predetermined level is approximately the voltage at ground.

11. The method of claim 8, wherein the tri-state buffer is switched in substantial synchronism with the first signal.

16. An I/O interface circuit for communicating across a transmission medium, comprising:

a first latch including

a first transmission input terminal, for receiving a first transmission signal to be transmitted via the transmission medium;

a first interface terminal, capable of connection to the transmission medium;

a first receive output terminal connected to the first interface terminal, for outputting a first receive signal received from the transmission medium;

a first buffer, having an output terminal connected to the first interface terminal, and a data input terminal; and

a first mode switch, having (i) two input terminals connected respectively to the first transmission input terminal and to the first receive output terminal, (ii) an output terminal connected to the first buffer'"'"'s data input terminal, and (iii) a mode select terminal capable of receiving a mode select signal for configuring the first mode switch to pass to the first buffer either the first transmission signal for transmission via the transmission medium or the first receive signal received from the transmission medium.

17. The I/O interface circuit of claim 16, further comprising

a storage device connected to the first buffer,

wherein when the first mode switch is configured to pass the first receive signal to the first buffer, the signal passed through the first mode select switch and input to the first buffer causes the first buffer to synchronously rectify the signal at the first interface terminal such that energy from the signal at the first interface terminal is stored in the storage device.

18. The I/O interface circuit of claim 16, further comprising

a voltage supply connected to the first buffer,

wherein when the first mode switch is configured to pass the first receive signal to the first buffer, the signal passed through the first mode select switch and input to the first buffer causes the first buffer to reinforce the signal appearing at the first interface terminal with energy from the voltage supply.

19. The I/O interface circuit of claim 16, wherein the first buffer further comprises:

a latch control terminal capable of receiving a latch control signal for enabling or disabling the first buffer.

20. The I/O interface circuit of claim 16, wherein the first buffer further comprises:

a complementary transistor pair connected between the data input terminal and the output terminal of the first buffer.

21. The I/O interface circuit of claim 20, wherein the first buffer is a tri-state buffer.

22. The I/O interface circuit of claim 16, further comprising:

a second transmission input terminal, for receiving a second transmission signal to be transmitted via the transmission medium;

a second interface terminal, capable of connection to the transmission medium;

a second receive output terminal connected to the second interface terminal, for outputting a second receive signal received from the transmission medium;

a second buffer, having an output terminal connected to the second interface terminal, and a data input terminal; and

a second mode switch, having (i) two input terminals connected respectively to the second transmission input terminal and to the second receive output terminal, (ii) an output terminal connected to the second buffer'"'"'s data input terminal, and (iii) a mode select terminal capable of receiving a mode select signal for configuring the second mode switch to pass to the second buffer either the second transmission signal for transmission via the transmission medium or the second receive signal received from the transmission medium.

23. The I/O interface circuit of claim 22, wherein the transmission medium is suitable for the transmission of a differential signal, and wherein the first and second receive signals and the first and second transmission signals form a differential receive signal and a differential transmission signal, respectively.