Single-transformer digital isolation barrier

• US 20070003055A1
• Filed: 06/23/2005
• Published: 01/04/2007
• Est. Priority Date: 06/23/2005
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Kiss, Peter, Bark, Boris, Yoder, James, Ransijn, Johannes, Grande, Brad
• Granted Patent: US 7,773,733 B2
• Time in Patent Office: Days
• US Class Current: 379/413
• CPC Class Codes: H04M 19/001 Current supply source at the exchanger providing current to substations

Abstract

The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.

Claims

1. A communication link, comprising:

an isolation barrier including a transformer having a system-side winding and a line-side winding;

a system-side interface circuit connected to the transformer'"'"'s system-side winding; and

a line-side interface circuit connected to the transformer'"'"'s line-side winding;

wherein the system-side interface circuit is capable of transmitting a signal across the transformer to the line-side interface circuit, the signal including (i) data content and (ii) energy to supply a substantial portion of the line-side interface circuit'"'"'s electrical load.

2. The communication link of claim 1, wherein the signal has an amount of energy that is greater than about 30% of the line-side interface circuit'"'"'s electrical load.

3. The communication link of claim 1, wherein the signal has an amount of energy that is one of at least a majority, at least a supermajority, and approximately the entirety of the electrical load of the line-side interface circuit.

4. The communication link of claim 1, wherein the signal has an amount of energy that is in the range of about 25 to about 100 milliwatts.

5. The communication link of claim 1, wherein the isolation barrier consists essentially of a single transformer.

6. The communication link of claim 1, wherein:

the line-side interface circuit comprises

a first line-side buffer having an output connected to the transformer'"'"'s line-side winding, and

a line-side receive buffer connected to the transformer'"'"'s line-side winding;

and

the system-side interface circuit comprises

a first system-side buffer having an output connected to the transformer'"'"'s system-side winding, and

a system-side receive buffer connected to the transformer'"'"'s system-side winding.

7. The communication link of claim 6, wherein:

the line-side interface circuit further comprises a second line-side buffer, and wherein the output of the first line-side buffer is connected to a first terminal of the transformer'"'"'s line-side winding and the output of the second line-side buffer is connected to a second terminal of the transformer'"'"'s line-side winding, such that the first and second line-side buffers form a differential line-side buffer; and

the system-side interface circuit further comprises a second system-side buffer, and wherein the output of the first system-side buffer is connected to a first terminal of the transformer'"'"'s system-side winding and the output of the second system-side buffer is connected to a second terminal of the transformer'"'"'s system-side winding, such that the first and second system-side buffers form a differential system-side buffer.

8. The communication link of claim 6, wherein the line-side interface circuit further comprises:

a line-side rectifier connected to the line-side winding of the transformer; and

a storage device connected to the line-side rectifier.

9. The communication link of claim 8, wherein the line-side rectifier is one of a half-wave diode bridge, a full-wave diode bride, and a synchronous rectifier.

10. A method of transferring data and power from a system-side circuit to a line-side circuit connected via an isolation barrier including a transformer having a system-side winding and a line-side winding, comprising the steps of:

inputting a first signal, comprising (i) data content and (ii) energy to supply a substantial portion of the line-side circuit'"'"'s electrical load, into the transformer'"'"'s system-side winding;

transforming the first signal at the transformer'"'"'s system-side winding to a first transformed signal at the transformer'"'"'s line-side winding;

providing a portion of the first transformed signal to a receive buffer; and

rectifying another portion of the first transformed signal to create a first rectified signal; and

storing the first rectified signal.

11. The method of claim 10, wherein the signal has an amount of energy that is greater than about 30% of the line-side interface circuits'"'"' electrical load.

12. The method of claim 10, wherein the signal has an amount of energy that is at least a majority, at least a supermajority, or approximately the entirety of the electrical load of the line-side interface circuit.

13. The method of claim 10, wherein the signal has an amount of energy that is in the range of about 25 to about 100 milliwatts.

14. The method of claim 10, wherein the isolation barrier consists essentially of a single transformer.

15. The method of claim 10, wherein the step of rectifying comprises the step of inputting the portion of the transformed signal into at least one of a half-wave diode bridge, a full-wave diode bridge, and a synchronous rectifier.

16. The method of claim 10, further comprising the steps of:

receiving a signal to be transmitted across the transformer; and

amplifying the signal to produce the first signal to be input into the transformer'"'"'s system-side winding.

17. A signal-powered integrated circuit, comprising:

an integrated circuit die including a ground node, a supply node, and a first terminal for receiving an input signal having data content and a predetermined energy;

a receive buffer formed on the integrated circuit die, connected to the first terminal and capable of receiving the data content associated with the input signal;

a rectifier formed on the integrated circuit die, the rectifier including

a first diode connected between the first terminal and the ground node, and

a second diode connected between the first terminal and the supply node,

wherein the rectifier is capable of rectifying the input signal and passing at least a portion of the input signal'"'"'s predetermined energy to the supply node, and

wherein each of the first and second diodes is capable of withstanding an ESD impulse.

18. The circuit of claim 17, wherein each diode in the rectifier is capable of withstanding an ESD impulse of at least about 1000 volts.

19. The circuit of claim 18, wherein each diode in the rectifier is capable of withstanding an ESD impulse in the range from about 1000 volts to about 2000 volts.

20. The circuit of claim 17, wherein the first and second diodes are parasitic diodes in a first transistor and a second transistor, respectively.

21. The circuit of claim 17, wherein the average energy of the input signal is sufficiently large to cause the first and second diodes to operate as a rectifier.

22. The circuit of claim 17, wherein the first and second diodes are the primary devices or the only devices that protect the integrated circuit die from electrostatic discharge through the first terminal.

23. The circuit of claim 17, wherein

the input signal is a differential input signal formed by a first signal and a second signal complementary to the first, and wherein the first terminal is capable of receiving the first signal;

the integrated circuit die further includes a second terminal capable of receiving the second signal; and

the rectifier further includes

a third diode connected between the second terminal and the ground node, and

a fourth diode connected between the second terminal and the supply node;

wherein the first, second, third and fourth diodes together provide full-wave rectification for the differential input signal, and

wherein each of the third and fourth diodes is capable of withstanding an ESD impulse.

24. A method of powering an integrated circuit, comprising the steps of:

receiving a first input signal having data content and a predetermined energy at a first terminal of the integrated circuit;

rectifying a portion of the first input signal via a first diode connected between the first terminal and a ground node of the integrated circuit, and a second diode connected between the first terminal and a supply node of the integrated circuit; and

storing at least a portion of the first input signal'"'"'s predetermined energy at the supply node;

wherein each of the first and second diodes is capable of withstanding an ESD impulse.

25. The circuit of claim 24, wherein each diode in the rectifier is capable of withstanding an ESD impulse of at least about 1000 volts.

26. The circuit of claim 24, wherein each diode in the rectifier is capable of withstanding an ESD impulse in the range from about 1000 volts to about 2000 volts.

27. The method of claim 24, wherein the first and second diodes are parasitic diodes in a first transistor and a second transistor, respectively.

28. The method of claim 24, wherein

the first input signal has an average energy that is sufficiently large to enable the rectifier to rectify the input signal.

29. The method of claim 24, further comprising the step of protecting the integrated circuit from electrostatic discharge through the first terminal essentially by the first and second diodes.

30. The method of claim 24, further comprising the step of buffering the data content associated with the first input signal.

31. The method of claim 24, further comprising the steps of:

receiving a second input signal having data content and a predetermined energy at a second terminal of the integrated circuit, the second input signal forming a differential input signal with the first input signal;

buffering the data content associated with the second input signal;

rectifying a portion of the second input signal via a third diode connected between the second terminal and the ground node of the integrated circuit, and a fourth diode connected between the second terminal and the supply node of the integrated circuit, each diode being capable of withstanding an ESD impulse; and

storing at least a portion of the second input signal'"'"'s predetermined energy at the supply node; and

thereby full-wave rectifying the differential input signal.