Method for containing a device and a corresponding device

• US 20070004096A1
• Filed: 06/26/2006
• Published: 01/04/2007
• Est. Priority Date: 12/24/2003
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Cavendish Kinetics Ltd. (Qorvo, Inc.)
• Inventors: Heuvelman, Willem
• Granted Patent: US 7,615,395 B2
• Time in Patent Office: Days
• US Class Current: 438/127
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81B 2207/096 through the substrate
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of enclosing a micromechanical element formed between a base layer and one or more metallization layers includes forming one or more encapsulating layers over the micromechanical element and providing an encapsulating wall surrounding the element extending between the base layer and the one or more encapsulating layers. An electrical connection is provided between the base layers and the one or more metallization layers formed above the micromechanical element.

Claims

1. A method of enclosing a micromechanical element formed between a base layer and one or more metallization layers comprising:

forming one or more encapsulating layers over at least part of the micromechanical element;

providing an encapsulating wall surrounding the element extending between the base layer and the one or more encapsulating layers; and

providing electrical connection between the base layers, and the one or more metallization layers formed above the micromechanical element.

2. The method according to claim 1 further comprising:

planarizing the one or more encapsulating layers;

forming one or more openings in the one or more encapsulating layers;

applying one or more sacrificial layers contacting the micromechanical element; and

removing the one or more sacrificial layers to expose the micromechanical element within a cavity.

3. The method according to claim 2, wherein the one or more openings formed in the one or more encapsulating layers are exposed using dry etching.

4. The method according to claim 2, wherein the planarizing recedes the one or more encapsulating layers closer to the one or more sacrificial layers.

5. The method according to claim 4, wherein the planarizing comprises chemical-mechanical polishing (CMP).

6. The method according to claim 2, wherein the one or more sacrificial layers comprise different forms of the same materials.

7. The method according to claim 2, wherein the one or more sacrificial layers comprise sacrificial materials comprising different materials.

8. The method according to claim 2, wherein the one or more sacrificial layers comprise an etchable silicon-based material.

9. The method according to claim 2, wherein one or more sacrificial layers is deposited using plasma enhanced chemical vapor deposition (PECVD).

10. The method according to claim 2, wherein removing the one or more sacrificial layers includes introducing an etchant through the one or more openings in the one or more encapsulating layers.

11. The method according to claim 10, wherein the etchant is a fluorine-based compound.

12. The method according to claim 2, wherein the one or more sacrificial layers comprise an etchable polymer-based material.

13. The method according to claim 12, wherein the one or more sacrificial layers is etched with an oxygen plasma.

14. The method according to claim 1, wherein the one or more encapsulating layers comprise silicon-based materials.

15. The method according to claim 1, wherein the encapsulating wall is formed from one or more stacked plugs.

16. The method according to claim 15, wherein the plugs provide electrical connection between the base layer and uppermost metallization layers of the underlying the micromechanical element.

17. The method according to claim 15, wherein the encapsulating wall extends through a dielectric layer and the encapsulating layers.

18. A method of forming a micromechanical element, comprising:

providing a base layer;

applying one or more sacrificial layers of an etchable material;

patterning the one or more sacrificial layers to define at least a portion of the shape of the micromechanical element;

applying at least one layer defining a mechanical material;

patterning the micromechanical element to form at least a portion of the micromechanical element; and

removing part of sacrificial layer to at least partly free the micromechanical element.

19. A semiconductor device comprising:

a micromechanical element formed on a base layer;

one or more encapsulating layers disposed over the micromechanical element; and

an encapsulating wall surrounding the micromechanical element extending from the base layer into the one or more encapsulating layers.