Transistor with improved tip profile and method of manufacture thereof

• US 20070004123A1
• Filed: 06/30/2005
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Rachmady, Willy, Murthy, Anand, Bohr, Mark, Keating, Steven, O'Neill, Donald, Letson, Thomas
• Granted Patent: US 7,494,858 B2
• Time in Patent Office: Days
• US Class Current: 438/230
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Claims

1. A method comprising:

forming an insulator on a substrate;

forming a gate on the insulator;

forming a plurality of sidewall spacers on the lateral surfaces of the gate; and

etching, with a wet etch, a source region and a drain region in the substrate, the wet etch substantially selective to a crystallographic plane in the substrate.

2. The method of claim 1 further comprising:

forming, with the wet etch, a facet in the {111} crystallographic plane of the substrate in the source region and a facet in the {111} crystallographic plane of the substrate in the drain region.

3. The method of claim 2 further comprising:

forming, with the wet etch, a facet in the {010} crystallographic plane of the substrate in the source region and a facet in the {010} crystallographic plane of the substrate in the drain region.

4. The method of claim 3 further comprising:

forming a source in the source region and a drain in the drain region.

5. The method of claim 4, the source and the drain further comprising silicon germanium.

6. The method of claim 5 wherein a surface of the source and a surface of the drain are substantially flush with the surface of the substrate.

7. The method of claim 1, a wet etch chemistry selected from the group consisting of NH₄OH, NH₃OH, TMAH, KOH, NaOH, BTMH, an amine-based etchant, and a combination thereof.

8. The method of claim 4, the wet etch chemistry having a pH of greater than approximately 9.0.

9. The method of claim 5, the substrate comprising {001} silicon.

10. A method comprising:

forming an insulator on a substrate;

forming a gate on the insulator;

forming a plurality of sidewall spacers on the lateral surfaces of the gate; and

etching, with a wet etch, a source region and a drain region in the substrate, the source region and the drain region each extending laterally beneath the gate, the source region and the drain region each further including

a facet in the {111} crystallographic plane of the substrate, and

a facet in the {010} crystallographic plane of the substrate.

11. The method of claim 10 further comprising:

forming a source in the source region and a drain in the drain region wherein a surface of the source and a surface of the drain are substantially flush with a surface of the substrate.

12. The method of claim 11 further comprising:

forming a silicide on the gate, on the source, and on the drain.

13. The method of claim 10, a wet etch chemistry selected from the group consisting of NH₄OH, NH₃OH, TMAH, KOH, NaOH, BTMH, an amine-based etchant, and a combination thereof.

14. The method of claim 11, the wet etch chemistry having a pH of greater than approximately 9.0.

15. The method of claim 10 wherein the substrate is {001} silicon.

16. A transistor comprising:

an insulator formed on a {001} silicon substrate;

a gate formed on the insulator;

a plurality of sidewall spacers formed on the lateral surfaces of the gate; and

a source and a drain formed in the substrate wherein a portion of the source and a portion of the drain each extend laterally beneath the gate and wherein the source and the drain each include a facet in the {111} crystallographic plane of the {001} silicon substrate.

17. The transistor of claim 16, the source and the drain each further comprising a facet in the {010} crystallographic plane of the {001} silicon substrate adjacent to the insulator.

18. The transistor of claim 17, each facet in the {010} crystallographic plane in the source and in the drain having a length of approximately 3 nanometers

19. The transistor of claim 17, the source and the drain each extending laterally beneath the gate by approximately 20 nanometers.

20. The transistor of claim 17, the source and the drain further comprising silicon germanium, wherein a surface of the source and a surface of the drain are each substantially flush with a surface of the {001} silicon substrate.