Transistor with improved tip profile and method of manufacture thereof
First Claim
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1. A method comprising:
- forming an insulator on a substrate;
forming a gate on the insulator;
forming a plurality of sidewall spacers on the lateral surfaces of the gate; and
etching, with a wet etch, a source region and a drain region in the substrate, the wet etch substantially selective to a crystallographic plane in the substrate.
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Abstract
Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.
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Citations
20 Claims
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1. A method comprising:
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forming an insulator on a substrate;
forming a gate on the insulator;
forming a plurality of sidewall spacers on the lateral surfaces of the gate; and
etching, with a wet etch, a source region and a drain region in the substrate, the wet etch substantially selective to a crystallographic plane in the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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forming an insulator on a substrate;
forming a gate on the insulator;
forming a plurality of sidewall spacers on the lateral surfaces of the gate; and
etching, with a wet etch, a source region and a drain region in the substrate, the source region and the drain region each extending laterally beneath the gate, the source region and the drain region each further including a facet in the {111} crystallographic plane of the substrate, and a facet in the {010} crystallographic plane of the substrate. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A transistor comprising:
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an insulator formed on a {001} silicon substrate;
a gate formed on the insulator;
a plurality of sidewall spacers formed on the lateral surfaces of the gate; and
a source and a drain formed in the substrate wherein a portion of the source and a portion of the drain each extend laterally beneath the gate and wherein the source and the drain each include a facet in the {111} crystallographic plane of the {001} silicon substrate. - View Dependent Claims (17, 18, 19, 20)
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Specification