SEMICONDUCTOR DEVICE HAVING FINFET AND METHOD OF FABRICATING THE SAME

• US 20070004129A1
• Filed: 06/29/2006
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Ju-Yong, CHUNG, Tae-Young, KIM, Yong-Sung, LEE, Kyu-Hyun
• Application Number:
  US11/427,734
• Publication Number:
  US 20070004129A1
• Time in Patent Office: Days
• US Class Current: 438/243
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In one embodiment, a semiconductor device includes a plurality of fin-shaped active regions defined by a trench formed in a substrate with a predetermined depth; an isolation layer formed inside the trench and comprising a first insulating material; and a plurality of word lines formed on the isolation layer inside the trench and covering a sidewall of the active region inside the trench. A separation layer is formed between two neighboring word lines to separate the two neighboring word lines of the plurality of word lines inside the trench with a predetermined distance. The separation layer comprises a second insulating material having an etch selectivity with respect to the first insulating material.

Claims

1. A semiconductor device comprising:

a plurality of fin-shaped active regions defined by a trench formed in a semiconductor substrate;

an isolation layer formed inside the trench, the isolation layer comprising a first insulating material;

a plurality of word lines formed on the isolation layer inside the trench, the plurality of word lines each covering a sidewall of the active region inside the trench;

a gate insulating layer formed between the active region and the word line; and

a separation layer formed between two adjacent word lines inside the trench, the separation layer comprising a second insulating material having an etch selectivity with respect to the first insulating material.

2. The semiconductor device according to claim 1, wherein the separation layer directly contacts a bottom surface of the trench.

3. The semiconductor device according to claim 1, wherein the separation layer is formed inside the trench with a shallower depth than that of the trench.

4. The semiconductor device according to claim 1, wherein the first insulating material comprises silicon oxide, and

the second insulating material comprises silicon nitride.

5. The semiconductor device according to claim 1, wherein the word line has a first surface facing the active region inside the trench, and has a second surface facing the separation layer inside the trench.

6. The semiconductor device according to claim 5, wherein the second surface of the word line directly contacts the separation layer.

7. The semiconductor device according to claim 1, wherein the active region is integrally formed with the semiconductor substrate.

8. The semiconductor device according to claim 1, wherein the active region extends along a first direction with an island shape;

and

the plurality of word lines extend along a second direction perpendicular to the first direction.

9. A method of fabricating a semiconductor device comprising:

partially etching the semiconductor substrate, thereby forming a trench to define fin-shaped active regions extending along a first direction in the semiconductor substrate;

forming an isolation layer comprising a first insulating material inside the trench;

partially removing the isolation layer, thereby forming a separation space inside the trench;

filling the inside of the separation space with a separation layer comprising a second insulating material having an etch selectivity with respect to the first insulating material;

partially removing the isolation layer, thereby forming a gate space between the separation layer and the active region inside the trench while exposing respective sidewalls of the separation layer and the active region;

forming a gate insulating layer on an upper surface and a sidewall of the active region; and

forming word lines filling the gate space on the gate insulating layer.

10. The method according to claim 9, wherein forming the separation space inside the trench comprises:

forming an etch mask pattern covering a predetermined region for the word lines on the isolation layer; and

etching a portion of the isolation layer exposed through the etch mask pattern.

11. The method according to claim 10, wherein forming the separation space is performed by etching the isolation layer until a bottom surface of the trench is exposed.

12. The method according to claim 10, wherein the etching is stopped before a bottom surface of the trench is exposed.

13. The method according to claim 10, wherein the semiconductor substrate is dry-etched to form the trench, using the hard mask pattern covering the active region as an etch mask.

14. The method according to claim 13, wherein the etch mask pattern is formed both on the isolation layer and the hard mask pattern;

and

the isolation layer is dry-etched to form the separation space inside the trench, using the hard mask pattern and the etch mask pattern as etch masks.

15. The method according to claim 13, wherein the isolation layer is etched back to form the gate space, using the separation layer and the hard mask pattern as etch masks.

16. The method according to claim 15, after forming the gate space, the method further comprises exposing an upper surface of the active region by removing the hard mask pattern.

17. The method according to claim 9, wherein the first insulating material comprises silicon oxide, and

the second insulating material comprises silicon nitride.

18. The method according to claim 9, wherein forming the gate insulating layer comprises thermally oxidizing an exposed surface of the active region.

19. The method according to claim 9, wherein the word lines are formed to extend in parallel with each other in a second direction that is perpendicular to the first direction.

20. The method according to claim 9, wherein each of the word lines covers an upper surface of the active region with the gate insulating layer between them, and covers a sidewall of the active region inside the gate space in the trench with the gate insulating layer between them.