Method for producing a vertical field effect transistor
First Claim
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1. A method for producing a vertical field effect transistor comprising the following steps:
- forming of at least one structure on a substrate which serves for forming the channel region of a field effect transistor;
applying an electrically insulating spacer layer near to the substrate after the formation of the structure;
applying an electrically conductive or semiconducting control electrode layer which serves for forming the control electrode of the field effect transistor planarization of the control electrode layer; and
whole-area etching-back of the planarized control electrode layer.
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Abstract
A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.
228 Citations
18 Claims
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1. A method for producing a vertical field effect transistor comprising the following steps:
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forming of at least one structure on a substrate which serves for forming the channel region of a field effect transistor;
applying an electrically insulating spacer layer near to the substrate after the formation of the structure;
applying an electrically conductive or semiconducting control electrode layer which serves for forming the control electrode of the field effect transistor planarization of the control electrode layer; and
whole-area etching-back of the planarized control electrode layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A vertical field effect transistor comprising a projection formed on a substrate for forming a channel region of a field effect transistor;
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a control electrode region of a control electrode of the field effect transistor formed on mutually opposite sides of the projection;
an insulating region arranged between the control electrode regions and the projection electrically insulating and adjoining the channel region;
a first connection region near the substrate at one end of the channel region; and
a second connection region remote from the substrate at the other end of the channel region, the control electrode having a planar interface which lies parallel to a base area of the projection near the substrate. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification