Receiver having digital automatic gain control

• US 20070004361A1
• Filed: 06/30/2005
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Piovaccari, Alessandro, Tuttle, G. Tyson, Srinivasan, Vishnu, Kasha, Dan
• Granted Patent: US 7,426,376 B2
• Time in Patent Office: Days
• US Class Current: 455/252.100
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/109 by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

An apparatus includes a semiconductor package, a radio receiver and a processor. The radio receiver is located in the semiconductor package and includes at least one gain stage. The processor is located in the semiconductor package to execute stored instructions to control the gain stage(s).

Claims

1. An apparatus comprising:

a semiconductor package;

a radio receiver located in the semiconductor package and comprising at least one gain stage; and

a processor located in the semiconductor package to execute stored instructions to control said at least one gain stage.

2. The apparatus of claim 1, wherein the semiconductor package comprises a die, and the radio receiver and the processor are fabricated on the die.

3. The apparatus of claim 1, wherein the gain stage comprises at least one of a radio frequency amplifier, an intermediate frequency amplifier and a digital filter.

4. The apparatus of claim 1, wherein said at least one gain stage comprises multiple gain stages, and the processor controls the multiple gain stages.

5. The apparatus of claim 1, further comprising:

multiple sense points within the receiver, wherein

the processor controls said at least one gain stage in response to feedback received from the multiple sensing points.

6. The apparatus of claim 5, wherein said at least one gain stage comprises multiple gain stages, and the multiple sense points are associated with gains of the multiple gain stages.

7. The apparatus of claim 5, further comprising:

at least one sensor to provide data for at least one of the sense points, wherein

the processor is adapted to at least partially power down said at least one sensor during periods of time in which the radio receiver is powered up and the processor is not using information provided by the sensor.

8. The apparatus of claim 1, further comprising:

a peak detector circuit to generate a signal indicative of a gain of said at least one gain stage, wherein

the processor is adapted to control said at least one gain stage in response to the signal.

9. The apparatus of claim 1, wherein the receiver comprises an analog-to-digital converter, and the processor controls the gain stage based on a status of an overload indication provided by the converter.

10. An apparatus comprising:

a radio frequency receiver having gain stages; and

a control unit shared in common by the gain stages to control gains of the gain stages.

11. The apparatus of claim 10, wherein the gain stages comprise at least one radio frequency gain stage and a lower frequency gain stage.

12. The apparatus of claim 11, the lower frequency gain stage comprises an intermediate frequency gain stage.

13. The apparatus of claim 10, wherein one of the gain stages comprises an amplifier to communicate a radio frequency signal.

14. The apparatus of claim 10, wherein one of the gain stages comprises an amplifier to communicate an intermediate frequency signal.

15. The apparatus of claim 10, wherein the gain stage comprises at least one of a radio frequency amplifier, an intermediate frequency amplifier and a comb filter.

16. A method comprising:

providing a digital processor in a semiconductor package that contains a radio receiver to control a gain of the receiver.

17. The method of claim 16, further comprising:

fabricating the radio receiver and the processor on a die shared in common.

18. The method of claim 16, further comprising:

using the processor to control at least one gain stage of the radio receiver.

19. The method of claim 16, wherein said at least one gain stage comprises multiple gain stages, the method further comprising:

adjusting a gain of each gain stage independently from the other gain stages.

20. The method of claim 19, further comprising:

providing multiple sensors in the radio receiver, and

configuring the processor to controls said at least one gain stage in response to feedback received from the multiple sensors.

21. The method of claim 20, further comprising:

powering down at least one of the sensors during periods of time in which the radio receiver is powered up and the processor is not controlling said at least one gain stage.

22. The method of claim 16, further comprising:

providing a peak detector circuit to generate a signal indicative of a gain of a gain stage of the radio receiver.

23. A radio frequency receiver, comprising:

an amplifier to receive a first radio frequency signal and provide a second radio frequency signal;

a mixer to translate the second radio frequency signal to a lower frequency signal;

an analog-to-digital converter to convert the lower frequency signal into a digital signal;

a digital signal processor to process the digital signal; and

a digital processor separate from the first digital signal processor to execute instructions to control a gain of the amplifier in response to a magnitude of the second radio frequency signal.

24. The radio frequency receiver of claim 23, further comprising:

a semiconductor package, wherein at least the processor, the mixer and the amplifier are part of the semiconductor package.

25. The radio frequency receiver of claim 23, wherein

the digital signal processor provides an indication of a strength of the digital signal, and

the digital processor controls the gain of the amplifier based on at least in part the indication.

26. The radio frequency receiver of claim 25, wherein the digital processor is further adapted to determine whether a change in the gain of the amplifier tracks a change in the indicated strength of the digital signal to determine whether intermodulation distortion is occurring.

27. The radio frequency receiver of claim 23, further comprising:

another amplifier to amplify the lower frequency signal, wherein digital processor executes instructions to control a gain of the lower frequency signal based on at least in part an output signal provided by said another amplifier.

28. The radio frequency receiver of claim 23, wherein the analog-to-digital signal is adapted to provide a signal indicative of an overload condition, and the digital processor controls the gain of the amplifier based in part on the presence of the signal.