METHOD AND APPARATUS FOR MONITORING INTEGRATED CIRCUIT TEMPERATURE THROUGH DETERMINISTIC PATH DELAYS

• US 20070005290A1
• Filed: 06/30/2005
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bueti, Serafino, Courchesne, Adam, Goodnow, Kenneth, Norman, Jason, Stanski, Stanley, Vento, Scott
• Granted Patent: US 7,275,011 B2
• Time in Patent Office: Days
• US Class Current: 702/130
• CPC Class Codes: G01K 3/10 in respect of time, e.g. reacting only to a quick change of temperature
• CPC Class Codes: G01K 3/14 in respect of space

Abstract

An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.

Claims

1. An apparatus for monitoring the temperature of an integrated circuit device, comprising:

a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored;

a deterministic signal source configured to generate a deterministic signal along said conductive wiring pattern;

one or more return paths tapped from selected locations along said conductive wiring pattern; and

a temperature change determination circuit coupled to said one or more return paths and to a reference signal taken from said deterministic signal source, said temperature change determination circuit configured to determine a delay between said reference signal and a delay signal traveling through at least a portion of said conductive wiring pattern and a corresponding one of said one or more return paths.

2. The apparatus of claim 1, wherein said temperature change determination circuit is further configured to compare a difference between a calibrated delay under nominal temperature conditions and a delay under elevated temperature conditions.

3. The apparatus of claim 2, wherein said temperature change determination circuit is further configured to isolate the location of one or more hot spots on the integrated circuit, depending on specific delay information received from said one or more return paths.

4. The apparatus of claim 3, wherein said conductive wiring pattern comprises a clock tree and said deterministic signal further comprises a clock signal.

5. The apparatus of claim 3, wherein said conductive wiring pattern comprises one or more fingers of a specified length and direction, each of said one or more fingers originating from said deterministic signal source.

6. The apparatus of claim 5, further comprising a plurality of deterministic signal sources having a corresponding set of one or more fingers originating therefrom.

7. The apparatus of claim 3, wherein said temperature change determination circuit further comprises:

an analog integrator configured to add to the magnitude of a difference signal between said reference signal and a corresponding delay signal, an output of said analog integrator representing a present delay value; and

a comparator for comparing said calibrated delay value, taken and stored from the output of said analog integrator during said nominal temperature conditions, with said present delay value.

8. The apparatus of claim 3, wherein said temperature determination circuit further comprises:

a digital device configured to generate a plurality of discrete delay values using said reference signal as a first input thereto, said digital device further receiving a corresponding delay signal a second input thereto and configured to compare said discrete delay values with said corresponding delay signal so as to determine a present delay value; and

a comparator for comparing said calibrated delay value, taken and stored from the output of said digital device during said nominal temperature conditions, with said present delay value.

9. The apparatus of claim 8, wherein said digital device further comprises:

a chain of delay buffers, a first one of which is coupled to said reference signal, wherein an output of each represents one of said plurality of discrete delay values; and

a comparator for comparing said delay signal to said discrete delay values an outputting a number of buffers to which said delay signal most closely matches.

10. The apparatus of claim 8, wherein said digital device further comprises:

a delay locked loop, coupled to said reference signal and configured to generate a plurality of output signals representing a plurality of discrete delay values; and

an edge detector configured to determine which of said discrete delay values said delay signal most closely matches.

11. A method for monitoring the temperature of an integrated circuit device, the method comprising:

defining a conductive wiring pattern on the integrated circuit device, extending into areas of the device to be monitored;

generating a deterministic signal along said conductive wiring pattern;

tapping one or more return paths from selected locations along said conductive wiring pattern; and

configuring a temperature change determination circuit coupled to said one or more return paths and to a reference signal taken from said deterministic signal source, said temperature change determination circuit configured to determine a delay between said reference signal and a delay signal traveling through at least a portion of said conductive wiring pattern and a corresponding one of said one or more return paths.

12. The method of claim 11, wherein said temperature change determination circuit is further configured to compare a difference between a calibrated delay under nominal temperature conditions and a delay under elevated temperature conditions.

13. The method of claim 12, wherein said temperature change determination circuit is further configured to isolate the location of one or more hot spots on the integrated circuit, depending on specific delay information received from said one or more return paths.

14. The method of claim 13, wherein said conductive wiring pattern comprises a clock tree and said deterministic signal further comprises a clock signal.

15. The method of claim 13, wherein said conductive wiring pattern comprises one or more fingers of a specified length and direction, each of said one or more fingers originating from said deterministic signal source.

16. The method of claim 15, further configuring a plurality of deterministic signal sources having a corresponding set of one or more fingers originating therefrom.

17. The method of claim 13, further comprising buffering outputs of said temperature change determination circuit for buffering for a determined period of time and outputting an average value therefrom.

18. The method of claim 13, further comprising defining a maximum temperature range of operation for the integrated circuit device.

19. The method of claim 13, wherein said calibrated delay is hard coded onto the integrated circuit device.

20. The method of claim 13, wherein said calibrated delay is generated during a power-on reset condition of the integrated circuit device.