Trainable hierarchical memory system and method
First Claim
1. A memory network of interconnected processing modules, comprising:
- a child processing module for receiving input data, the child processing module generating lower level characterization data that represent patterns and/or sequences found in the input data, the child module outputting the lower level characterization data;
a parent processing module for receiving the lower level characterization data, the parent processing module generating higher level characterization data that represent patterns and/or sequences found in the lower level characterization data;
the parent module providing feedback to the child module for linking the higher level characterization data to the lower level characterization data.
1 Assignment
0 Petitions
Accused Products
Abstract
Memory networks and methods are provided. Machine intelligence is achieved by a plurality of linked processor units in which child modules receive input data. The input data are processed to identify patterns and/or sequences. Data regarding the observed patterns and/or sequences are passed to a parent module which may receive as inputs data from one or more child modules. the parent module examines its input data for patterns and/or sequences and then provides feedback to the child module or modules regarding the parent-level patterns that correlate with the child-level patterns. These systems and methods are extensible to large networks of interconnected processor modules.
-
Citations
26 Claims
-
1. A memory network of interconnected processing modules, comprising:
-
a child processing module for receiving input data, the child processing module generating lower level characterization data that represent patterns and/or sequences found in the input data, the child module outputting the lower level characterization data;
a parent processing module for receiving the lower level characterization data, the parent processing module generating higher level characterization data that represent patterns and/or sequences found in the lower level characterization data;
the parent module providing feedback to the child module for linking the higher level characterization data to the lower level characterization data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method for training a memory network comprising the step of:
-
receiving training data comprising a world of patterns at a child processing module;
generating lower level characterization data that represent the patterns in the input data, outputting the lower level characterization data to a parent module;
generating higher level characterization data that represent patterns in the lower level characterization data;
providing feedback to the child module for linking the higher level characterization data to the lower level characterization data. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
-
21. An interpretive framework method for training a memory system, comprising the steps of:
-
processing a discrete stream of input data at each of two or more lower tier processing modules, wherein the processing at each lower tier processing module comprises identifying and labeling lower tier patterns and/or sequences in the input data stream;
passing the lower tier sequence identity label from each the two or more lower tier processing modules to an upper tier processing module;
processing the lower tier sequence identity label data in the upper tier processing module, the processing of the lower tier sequence identity label data comprising identifying and labeling upper tier sequences and quantifying the relative and/or absolute frequency of the upper tier sequences; and
providing feedback to the lower tier modules regarding the relative and/or absolute frequency of one of the upper tier sequences in relation to the occurrence of a specific lower tier sequence. - View Dependent Claims (22, 23, 24)
-
-
25. A data processing structure, comprising:
-
an upper tier processing module;
a first and a second lower tier processing module, each of which receives a discrete stream of input data, the first and the second lower tier processor modules each comprising a memory and a processor that categorizes the received input data into discrete categories and identifies, labels, and quantifies the relative and/or absolute frequency of sequences observed in the categorized input data;
two-way links that separately connect the first lower tier processing module to the upper tier processing module and the second lower tier processing module to the upper tier processing module.
-
-
26. A memory network, comprising:
-
a first lower tier processing module having a first receptive field size and a second lower tier processing module having a second receptive field size;
an upper tier processing module having a third receptive field size that at least as large as the sum of the first and the second receptive field sizes;
external inputs feeding a discrete input data stream to each of the first and the second lower tier processing modules;
data links between the upper tier processing module and the lower tier processing modules, wherein each data link passes processed lower tier sequence information from one of the first tier processing modules to the second tier processing module and feedback information from the second tier module to the one first tier processing module, the lower tier sequence information comprising an identity label and a relative and/or absolute frequency for each data sequence experienced by the one first tier processing module and the feedback information comprising a relative and/or absolute frequency correlation between each data sequence experienced by the one first tier processing module and a second tier sequence experienced by the second tier module.
-
Specification