Data transfer control device and electronic instrument

• US 20070005851A1
• Filed: 06/23/2006
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Abandoned Application

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Kobayashi, Nobuharu, Oshita, Shun
• Application Number:
  US11/473,013
• Publication Number:
  US 20070005851A1
• Time in Patent Office: Days
• US Class Current: 710/74
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A data transfer control device includes an ATA device-side I/F which transfers data between the data transfer control device and an ATA host through a bus ATABUS1, an ATA host-side I/F which transfers data between the data transfer control device and an ATA host through a bus ATABUS2, device-side pads which are pads for the device-side I/F, host-side pads which are pads for the host-side I/F, and a switching circuit including switching elements which connect or disconnect signal lines from the device-side pads and signal lines from the host-side pads.

Claims

1. A data transfer control device comprising:

an ATA device-side interface which transfers data between the data transfer control device and an ATA host through a first ATA bus;

an ATA host-side interface which transfers data between the data transfer control device and an ATA device through a second ATA bus;

first to Nth device-side pads connected with first to Nth signal lines of the first ATA bus, the first to Nth device-side pads being pads for the device-side interface;

first to Nth host-side pads connected with first to Nth signal lines of the second ATA bus, the first to Nth host-side pads being pads for the host-side interface; and

a switching circuit including first to Nth switching elements which connect or disconnect signal lines from the first to Nth device-side pads and signal lines from the first to Nth host-side pads.

2. The data transfer control device as defined in claim 1, comprising:

first to Nth device-side I/O cells connected with the signal lines from the first to Nth device-side pads, the first to Nth device-side I/O cells being I/O cells for the device-side interface; and

first to Nth host-side I/O cells connected with the signal lines from the first to Nth host-side pads, the first to Nth host-side I/O cells being I/O cells for the host-side interface;

wherein the Mth (1≦

M≦

N) switching element of the first to Nth switching elements is disposed between the Mth device-side I/O cell of the first to Nth device-side I/O cells and the Mth host-side I/O cell of the first to Nth host-side I/O cells.

3. The data transfer control device as defined in claim 1, wherein the first to Nth device-side pads and the first to Nth host-side pads are disposed so that the Lth (1≦

L<

N) host-side pad is positioned adjacent to the Lth device-side pad, the (L+1)th device-side pad is positioned adjacent to the Lth host-side pad, and the (L+1)th host-side pad is positioned adjacent to the (L+1)th device-side pad.

4. The data transfer control device as defined in claim 1, wherein the first to Nth device-side pads and the first to Nth host-side pads are disposed so that the Lth (1≦

L<

N) host-side pad is positioned adjacent to the Lth device-side pad, the (L+1)th host-side pad is positioned adjacent to the Lth host-side pad, and the (L+1)th device-side pad is positioned adjacent to the (L+1)th host-side pad.

5. The data transfer control device as defined in claim 1, comprising:

a processing section which controls the switching circuit;

wherein, when the processing section has determined that the data transfer control device has been set in a hard wired mode, the processing section turns ON the first to Nth switching elements to connect the signal lines from the first to Nth device-side pads and the signal lines from the first to Nth host-side pads.

6. The data transfer control device as defined in claim 5, comprising:

a register into which a command issued by the ATA host is written through the first ATA bus;

wherein the processing section determines whether or not the data transfer control device has been set in the hard wired mode based on the command written into the register.

7. The data transfer control device as defined in claim 6, wherein the register is a task register included in the device-side interface.

8. The data transfer control device as defined in claim 6, wherein, when a mode setting command assigned to a vender specific command has been written into the register, the processing section determines whether or not the data transfer control device has been set in the hard wired mode based on the vender specific mode setting command written into the register.

9. The data transfer control device as defined in claim 5, wherein the processing section performs emulation processing for transferring data between the ATA host and the ATA device through the first and second ATA buses.

10. The data transfer control device as defined in claim 1, comprising:

a first interface which transfers data through a first bus; and

a transfer controller which controls data transfer among the device-side interface, the host-side interface, and the first interface.

11. The data transfer control device as defined in claim 10, comprising:

an ATA second host-side interface which transfers data between the data transfer control device and an ATA device through a third ATA bus;

wherein the transfer controller controls data transfer among the device-side interface, the host-side interface, the second host-side interface, and the first interface.

12. The data transfer control device as defined in claim 10, wherein the first interface includes a physical layer circuit which at least either transmits or receives data through a serial bus.

13. The data transfer control device as defined in claim 10, wherein the first bus is a Universal Serial Bus (USB) bus, and the first interface is a USB interface.

14. The data transfer control device as defined in claim 10, comprising:

first to Kth (K≧

2) interfaces which transfer data through first to Kth buses;

wherein the transfer controller controls data transfer among the device-side interface, the host-side interface, and the first to Kth interfaces.

15. An electronic instrument comprising:

the data transfer control device as defined in claim 1;

the ATA host connected with the data transfer control device through the first ATA bus; and

the ATA device connected with the data transfer control device through the second ATA bus.

16. An electronic instrument comprising:

the data transfer control device as defined in claim 2;

the ATA host connected with the data transfer control device through the first ATA bus; and

the ATA device connected with the data transfer control device through the second ATA bus.

17. An electronic instrument comprising:

the data transfer control device as defined in claim 3;

the ATA host connected with the data transfer control device through the first ATA bus; and

the ATA device connected with the data transfer control device through the second ATA bus.

18. An electronic instrument comprising:

the data transfer control device as defined in claim 4;

the ATA host connected with the data transfer control device through the first ATA bus; and

the ATA device connected with the data transfer control device through the second ATA bus.

19. An electronic instrument comprising:

the data transfer control device as defined in claim 5;

the ATA host connected with the data transfer control device through the first ATA bus; and

the ATA device connected with the data transfer control device through the second ATA bus.

20. An electronic instrument comprising:

the data transfer control device as defined in claim 10;

the ATA host connected with the data transfer control device through the first ATA bus; and

the ATA device connected with the data transfer control device through the second ATA bus.