Fully buffered DIMM variable read latency

• US 20070005922A1
• Filed: 06/30/2005
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Thomas, Tessil, Swaminathan, Muthukumar, Vogt, Pete
• Application Number:
  US11/173,641
• Publication Number:
  US 20070005922A1
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

Memory control that access memory devices having different read latencies is described. In on embodiment, a memory controller may include read latency logic to identify and match received read data with read commands to the memory devices based on values indicative of the read latency for the memory devices. In another embodiment, the memories may include read delay control to insert an amount of delay into the time a memory device takes in responding to a read command.

Claims

1. An apparatus comprising:

a storage to store a plurality of values, each of the plurality of values indicative of read latency for a memory device in a plurality of memory devices;

a read request queue to store read requests; and

read latency logic coupled to the storage and the read request queue to identify each set of received read data as matching to a read command to one of the plurality memory devices based on the plurality of values.

2. The apparatus defined in claim 1 further comprising a read reorder buffer, responsive to read commands ordered in the read request buffer, to reorder received read data into an order in which the read commands were received into the read request queue.

3. The apparatus defined in claim 1 further comprising request reorder logic.

4. A memory device comprising:

a storage array; and

interface logic coupled to the storage array and responsive to read and write requests, wherein the interface logic comprises read delay control to insert an amount of delay in responding to a read command.

5. The memory device defined in claim 4 wherein the amount of delay is programmable.

6. The memory device defined in claim 4 wherein the storage array is part of a dual in-line memory module (DIMM).

7. A method comprising:

reading a stored value for a memory device to determine when a response of read data to read commands is to be expected, the value being indicative of the read latency for the corresponding memory device; and

identifying received read data received as corresponding to a read command to the memory device based on the value.

8. The method defined in claim 7 further comprising determining the read latency of each of the plurality of memory devices.

9. The method defined in claim 7 further comprising storing a value for each of the plurality of memory devices.

10. The method defined in claim 7 wherein identifying received read data received as corresponding to a read command to the memory device is also based on the received read data.

11. A method comprising:

determining read latency of each of the plurality of memory devices;

configuring at least one of the plurality of memory devices based on the determined read latency values; and

identifying received read data received as corresponding to a read command to one of the plurality of memory devices based on a value indicative of its read latency.

12. The method defined in claim 11 wherein configuring at least one of the plurality of memory devices comprises inserting a delay to increase a read latency of one of the plurality of memory devices.

13. The method defined in claim 12 wherein the delay increases the read latency to match the longest read latency of memory devices in the plurality of memory devices.

14. The method defined in claim 12 wherein the delay increases the read latency to match the shortest read latency of memory devices in the plurality of memory devices.

15. The method defined in claim 11 wherein configuring at least one of the plurality of memory devices comprises inserting delays to cause all memory devices in the plurality of memory devices to have a common read latency.