Technique to write to a non-volatile memory

• US 20070005928A1
• Filed: 06/30/2005
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Coulson, Rick, Matthews, Jeanna, Faber, Robert, Trika, Sanjeev
• Granted Patent: US 7,797,479 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers

Abstract

A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

Claims

1. A method comprising:

performing a plurality of write operations to store data in different physical memory locations, each of the physical memory locations being associated with a logical address shared in common among the physical memory locations; and

storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

2. The method of claim 1, wherein the sequence information comprises one of a global sequence number, a local sequence number and a timestamp.

3. The method of claim 1, further comprising:

storing the logical address in the physical memory locations to indicate which one of the write operations occurred last.

4. The method of claim 1, wherein each physical memory location stores a different version of data for the logical address.

5. The method of claim 1, further comprising:

storing an indication of the logical address in each physical memory location.

6. The method of claim 1, wherein the physical memory locations are part of a non-volatile memory, the method further comprising:

in response to each of the write operations, updating status information in a volatile memory to indicate which one of the physical memory locations stores valid data.

7. The method of claim 1, wherein the physical memory locations are part of a non-volatile memory, the method further comprising:

in response to each of the write operations, updating a logical-to-physical address translation table indicative of a mapping between the logical address and one of the physical memory locations.

8. The method of claim 7, further comprising:

erasing the indicated physical memory location in a block erase operation.

9. The method of claim 1, further comprising:

in response to a power failure, using the sequence information to reconstruct a logical-to-physical translation table indicative of a mapping between the logical address and one of the physical memory locations.

10. The method of claim 1, further comprising:

in response to a power failure, using the sequence information to determine which of the physical memory locations do not store valid data for the logical address.

11. The method of claim 1, further comprising:

in response to a power failure, using the sequence information to determine which of the physical memory locations are in a blank state and which of the physical memory locations are used.

12. An apparatus comprising:

a non-volatile memory; and

a controller coupled to the memory to;

perform a plurality of write operations to store data in different physical memory locations of the non-volatile memory, each of the physical memory locations being associated with a logical address shared in common among the physical memory locations, and

store sequence information in the physical memory locations to indicate which one of the write operations occurred last.

13. The apparatus of claim 12, wherein the sequence information comprises one of a global sequence number, a local sequence number and a timestamp.

14. The apparatus of claim 12, wherein the controller stores the logical address in the physical memory locations.

15. The apparatus of claim 12, wherein each physical memory location stores a different version of data for the logical address.

16. The apparatus of claim 12, wherein the controller stores an indication of the logical address in each physical memory location.

17. The apparatus of claim 16, further comprising:

a volatile memory, wherein

the controller in response to each of the write operations, updates status information in a volatile memory to indicate which one of the physical memory locations stores valid data.

18. The apparatus of claim 16, further comprising:

a volatile memory, wherein

the controller in response to each of the write operations, updates a logical-to-physical address translation table indicative of a mapping between the logical address and one of the physical memory locations.

19. The apparatus of claim 12, wherein the controller in response to a power failure, uses the sequence information to reconstruct a logical-to-physical translation table indicative of a mapping between the logical address and one of the physical memory locations.

20. A system comprising:

a non-volatile memory;

a dynamic random access memory; and

a controller to;

use a logical-to-physical address translation table stored in the dynamic random access memory to perform a plurality of write operations to store data in different physical memory locations of the non-volatile memory, each of the physical memory locations being associated with a logical address shared in common among the physical memory locations, and

store sequence information in the physical memory locations to indicate which one of the write operations occurred last.

21. The system of claim 20, wherein the controller in response to a power failure, uses the sequence information to reconstruct the logical-to-physical address translation table.

22. The system of claim 20, wherein the controller in response to a power failure, uses the sequence information to determine which of the physical memory locations do not store valid data for the logical address.

23. An article comprising a computer accessible storage medium storing instructions to, when executed, cause the computer to:

perform a plurality of write operations to store data in different physical memory locations, each of the physical memory locations being associated with a logical address shared in common among the physical memory locations; and

store sequence information in the physical memory locations to indicate which one of the write operations occurred last.

24. The article of claim 23, the storage medium storing instructions to, when executed, cause the computer to store an indication of the logical address in each physical memory location.

25. The article of claim 23, the storage medium storing instructions to, when executed, cause the computer to in response to each of the write operations, update status information in a volatile memory to indicate which one of the physical memory locations is currently associated with the logical address.

26. The article of claim 23, wherein the physical memory locations are part of a non-volatile memory, the storage medium storing instructions to, when executed, cause the computer to in response to each of the write operations, update a logical-to-physical address translation table indicative of a mapping between the logical address and one of the physical memory locations.

27. The article of claim 23, the storage medium storing instructions to, when executed, cause the computer to in response to a power failure, use the sequence numbers to reconstruct a logical-to-physical translation table indicative of a mapping between the logical address and one of the physical memory locations.

28. The article of claim 23, the storage medium storing instructions to, when executed, cause the computer to in response to a power failure, use the sequence information to determine which of the physical memory locations do not store valid data for the logical address.

29. The article of claim 23, the storage medium storing instructions to, when executed, cause the computer to in response to a power failure, use the sequence numbers to determine which of the physical memory locations are erased.