Method and apparatus for predicting memory failure in a memory system

• US 20070006048A1
• Filed: 06/29/2005
• Published: 01/04/2007
• Est. Priority Date: 06/29/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bulusu, Mallik, Khanna, Rahul, Rothman, Michael, Zimmer, Vincent, Goud, Gundrala, Rai, Satish
• Application Number:
  US11/169,408
• Publication Number:
  US 20070006048A1
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G06F 11/008 Reliability or availability analysis

Abstract

A method for managing a memory system includes comparing one or more conditions of a memory with historical memory data that predicts a future state of the memory. According to one embodiment, updating the historical memory data includes accumulating operation data on the memory during its operation, generating updated historical memory data with the operation data, and updating the historical memory data with the updated historical memory data. Other embodiments are described and claimed.

Claims

1. A method for managing a memory system, comprising:

comparing one or more conditions of a memory with historical memory data that predicts a future state of the memory.

2. The method of claim 1, further comprising updating the historical memory data.

3. The method of claim 2, wherein updating the historical memory data comprises:

accumulating operation data on the memory during its operation;

generating updated historical memory data with the operation data; and

updating the historical memory data with the updated historical memory data.

4. The method of claim 3, wherein generating updated historical memory data with the operation data comprises performing a Bayes statistical analysis.

5. The method of claim 2, wherein updating the historical memory data comprises retrieving updated historical memory data external from the memory system.

6. The method of claim 1, further comprising migrating the memory if the future state is memory failure.

7. The method of claim 1, further comprising generating a notification if the future state is memory failure.

8. The method of claim 1, wherein the historical memory data comprises probabilities of future states from manufacturing data.

9. The method of claim 1, wherein the historical memory data comprises probabilities of future states from field data.

10. The method of claim 1, wherein the historical memory data comprises probabilities of future states from operation data.

11. An article of manufacture comprising a machine accessible medium including sequences of instructions, the sequences of instructions including instructions which when executed cause the machine to perform:

comparing one or more conditions of a memory with historical memory data that predicts a future state of the memory.

12. The article of manufacture of claim 11, further comprising instructions which when executed cause the machine to perform updating the historical memory data.

13. The article of manufacture of claim 12, wherein updating the historical memory data comprises:

accumulating operation data on the memory during its operation;

generating updated historical memory data with the operation data; and

updating the historical memory data with the updated historical memory data.

14. The article of manufacture of claim 13, wherein generating updated historical memory data with the operation data comprises performing a Bayes statistical analysis.

15. The article of manufacture of claim 12, wherein updating the historical memory data comprises retrieving updated historical memory data external from the memory system.

16. A computer system, comprising:

a processor;

a memory; and

a prediction module to compare one or more conditions of the memory with historical memory data that predicts a future state of the memory.

17. The computer system of claim 16, wherein the prediction module further comprises a data maintenance unit to update the historical memory data with operation data from the memory.

18. The computer system of claim 16, wherein the prediction module further comprises a response unit to initiate migration of the memory in response to a memory failure prediction.

19. The computer system of claim 16, wherein the prediction module is implemented in a basic input output system and executed by the processor.

20. The computer system of claim 16, wherein the prediction module is implemented in an application and executed on an out of band processor.