Input threshold adjustment in a synchronous data sampling circuit

• US 20070006054A1
• Filed: 07/01/2005
• Published: 01/04/2007
• Est. Priority Date: 07/01/2005
• Status: Active Grant

• Current Assignee: SLT Logic LLC
• Original Assignee: SLT Logic LLC
• Inventors: Fiedler, Alan
• Granted Patent: US 7,573,967 B2
• Time in Patent Office: Days
• US Class Current: 714/709
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A data sampler system receives a high-speed data stream and uses a first set of data samplers for sampling the data stream at a first set of clock phase angles to produce a first set of sequential data “eye” samples. A second set of data samplers, to sampled at a second set of clock phase angles that are different from the first set of clock phase angles to produce a second set of sequential data transition samples. The first set of data samplers, the data stream is sampled at the second set of clock phase angles to produce a third set of sequential data transition samples and with the second set data samplers, the data stream is sampled at a first set of clock phase angles to produce a fourth set of sequential data “eye” samples. The system alternates between the first mode and a second mode in which the results produce a reduced input offset voltage for the sampler system.

Claims

1. A data sampling system, comprising:

a first set of data samplers and a second set of data samplers, each set of data samplers having an adjustable quantization threshold;

a mode sub-system adapted to selectively facilitate mode switching between a first mode and second mode of operation, the first mode of operation causing the first set of data samplers to equate for data transition sampling and the second set of data samplers to operate for data eye sampling, and the second mode of operation causing the first set of data samplers to operate for data eye sampling and the second set of data samplers to operate for data transition sampling in a second mode; and

a threshold adjustment sub-system adapted to adjust at least one quantization threshold for at least one of the first and second sets of data samplers.

2. The data sampling system of 1, wherein the threshold adjustment sub-system is adapted to independently adjust the quantization threshold for each of the first and the second sets data samplers.

3. The data sampling system of 1, wherein the threshold adjustment sub-system is adapted to adjust the quantization threshold for the one of the first and the second sets of data samplers hat is operating for data transition sampling.

4. The data sampling system of 1, wherein the at least one quantization threshold represents an amplitude distinguishing a first and a second binary logic state.

5. The data sampling system of 1, wherein the threshold adjustment sub-system is adapted to adjust the at least one quantization threshold based on consecutive samples of the data eye sampling.

6. The data sampling system of 5, wherein the threshold adjustment sub-system is adapted to adjust the at least one quantization threshold based on a data transition having occurred sequentially between the consecutive samples of the data eye sampling.

7. The data sampling system of 1, wherein the threshold adjustment sub-system is adapted to adjust the at least one quantization threshold to increase a likelihood that a subsequent data transition will be detected.

8. The data sampling system of 1, wherein the threshold adjustment sub-system is adapted to adjust the at least one quantization threshold to increase a likelihood that, in response to a detected subsequent data transition, an output data state of a data sampler toggles with respect to a previous output data state of the data sampler.

9. The data sampling system of 1, and further comprising:

a plurality of clock signals having their phase angles distributed over 360 degrees;

wherein the mode sub-system changes from a first clocking signal set for the first mode to a second clocking signal set having a different set of phase angles from the first clocking signal set for the second mode.

10. A method of receiving a high-speed data stream, the method comprising:

sampling, with a first data sampler set, the data stream at a first set of clock phase angles to produce a first set of sequential data eye samples;

sampling, with a second data sampler set, the data stream at a second set of clock phase angles that are different from the first set of clock phase angles to produce a second set of sequential data transition samples;

sampling, with the first data sampler set, the data stream at the second set of clock phase angles to produce a third set of sequential data transition samples;

sampling, with the second data sampler set, the data stream at a first set of clock phase angles to produce a fourth set of sequential data eye samples.

11. The method of claim 10, and further comprising:

based at least on the first and third sets of samples, adjusting an input quantization threshold of the first data sampler set.

12. The method of claim 10, and further comprising:

multiplexing samples to produce a recovered data output that includes the first and fourth sets of data eye samples.

13. A data sampling circuit, comprising:

a serial data input;

at least a pair of data samplers adapted to sample the serial data, each having an adjustable input threshold;

means for supplying phase angle-selectable clock signaling to the data samplers such that the data samplers are individually configurable for data eye sampling or for data transition sampling;

means for incrementally adjusting the input threshold for each data sampler based at least in part on previous data samples.

14. The data sampling circuit of claim 13, wherein the adjustment means are adapted to adjust the input threshold for each data sampler so as to increase a sensitivity of each data sampler to a future data transition.

15. The data sampling circuit of claim 13, and further comprising:

means for selecting between individual data samplers to provide a recovered data output that includes alternating samples from different data samplers.

16. The data sampling circuit of claim 13, further comprising control means for operating at least a pair of data samplers in alternating modes of data eye sampling and data transition sampling.