Hierarchical presentation techniques for a design tool

• US 20070006112A1
• Filed: 09/08/2006
• Published: 01/04/2007
• Est. Priority Date: 04/20/2001
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Gutberlet, Peter, Waters, Simon, Bowyer, Bryan
• Granted Patent: US 7,712,050 B2
• Time in Patent Office: Days
• US Class Current: 716/102
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06Q 10/06312 Adjustment or analysis of established resource schedule, e.g. resource or task levelling, or dynamic rescheduling
• CPC Class Codes: G06Q 10/06313 Resource planning in a project environment
• CPC Class Codes: Y10S 715/963 Calendar or scheduling
• CPC Class Codes: Y10S 715/964 CAD or CAM, e.g. interactive design tools

Abstract

A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.

Claims

1. In a design tool, a method comprising:

displaying a top-level schedule for a design that includes one or more loops; and

displaying a first loop schedule for a first loop of the one or more loops, wherein timing within the first loop schedule is presented relative to the first loop schedule, and wherein timing within the top-level schedule is presented relative to the top-level schedule.

2. The method of claim 1 wherein the displaying the first loop schedule hierarchically nests the first loop schedule within the top-level schedule.

6. The method of claim 1 further comprising:

hiding the first loop schedule responsive to a command from a designer.

7. The method of claim 1 further comprising:

displaying a textual list of scheduled operations; and

displaying an icon adjacent a first loop label in the textual list, the icon indicating whether the first loop schedule is expanded or collapsed.

9. The method of claim 1 wherein the top-level schedule includes at least one pseudo-operation icon.

10. The method of claim 1 wherein the first loop includes plural alternative branches of execution having different lengths.

11. The method of claim 1 wherein the design tool is a behavioral synthesis tool.

12. A computer-readable medium storing computer-executable instructions for causing a computer programmed thereby to perform the method of claim 1.

42. The method of claim 1 wherein the design tool is an electronic circuit design tool or system design tool, and wherein the design is an electronic circuit design or system design.

3-5. -5. (canceled)

8. (canceled)

13. In a design tool, a method of presenting information for a design, the method comprising:

presenting first information for a block of a design, the block including a sub-block nested within the block of the design; and

presenting second information for the sub-block of the design, wherein timing within the block is presented as independent of timing within the sub-block, and wherein the timing within the sub-block is presented as independent of the timing within the block.

14. The method of claim 13 wherein the block is for a top-level loop, wherein the top-level loop includes a nested loop, and wherein the sub-block is for the nested loop.

15. The method of claim 13 wherein the sub-block is for one of plural alternative branches of execution within the block.

16. The method of claim 13 wherein the first information is a block schedule and the second information is a sub-block schedule.

17. The method of claim 13 wherein the first information is a block schedule and the second information is an icon representing a sub-block schedule.

18. The method of claim 17 wherein the icon appears in a clock overhead space of a step of the block schedule.

19. The method of claim 13 wherein timing within the sub-block is presented relative to the sub-block.

20. The method of claim 13 wherein control steps indicate the timing within the block and the timing within the sub-block, and wherein each of the block and the sub-block includes an independently numbered set of control steps.

21. The method of claim 13 wherein the presenting the second information nests the second information within the first information.

22. The method of claim 16 further comprising presenting the sub-block schedule in a separate window.

23. The method of claim 13 further comprising:

presenting a list of operation labels including one or more sub-block operation labels indented relative to one or more block operation labels in the list.

24. The method of claim 13 further comprising:

presenting third information for a second sub-block of the design, wherein the timing within the block is presented as independent of timing within the second sub-block, and wherein the timing within the second sub-block is presented as independent of the timing within the block.

25. The method of claim 13 wherein the design tool is a behavioral synthesis tool.

26. A computer-readable medium storing computer-executable instructions for causing a computer programmed thereby to perform the method of claim 13.

43. The method of claim 13 wherein the design tool is an electronic circuit design tool or system design tool, and wherein the design is an electronic circuit design or system design.

44. The method of claim 13 wherein the timing within the block is presented as independent in that the second information is presented within a single control step of the block regardless of number of control steps of the sub-block.

45. The method of claim 13 wherein the sub-block includes a sub-sub-block, the method further comprising presenting third information for the sub-sub-block, wherein the timing within the block, the timing within the sub-block, and the timing within the sub-sub-block are presented as being independent of each other.

46. The method of claim 17 wherein the icon is presented in a scheduling frame that shows allowable locations of the sub-block schedule within the block schedule.

27. In a design tool, a method comprising:

presenting plural nested schedules for a design, each of the plural nested schedules including;

a line of control step labels, wherein control step timing for each of the plural nested schedules is relative to that nested schedule; and

one or more lines of schedule information including at least one operation icon.

28. The method of claim 27 wherein the plural nested schedules include a top-level schedule, and wherein presentation of each of the plural nested schedules other than the top-level schedule is in a clock overhead space of a control step of the schedule enclosing the nested schedule.

29. The method of claim 27 wherein presentation of each of the plural nested schedules expands or collapses responsive to designer input.

30. The method of claim 27 wherein the design tool is a behavioral synthesis tool.

47. The method of claim 27 wherein the design tool is an electronic circuit design tool or system design tool, and wherein the design is an electronic circuit design or system design.

48. The method of claim 27 wherein each of the at least one operation icon represents a scheduled operation.

31. In an electronic circuit design tool or system design tool, a method of presenting a list of operations for an electronic circuit design or system design, the method comprising:

presenting a top-level list of one or more operations for the design, wherein the top-level list includes a first loop label for a first nested loop; and

presenting a sub-list of one or more operations for the first nested loop, wherein the sub-list is indented relative to the top-level list.

32. The method of claim 31 further comprising:

responsive to a collapse command, hiding the sub-list.

33. The method of claim 31 wherein the design tool is a behavioral synthesis tool.

34. A computer-readable medium storing computer-executable instructions for causing a computer programmed thereby to perform the method of claim 31.

35. In an electronic circuit design tool or system design tool, a method of presenting a list of operations for an electronic circuit design or system design, the method comprising:

presenting a top-level list of one or more operations for the design, wherein the top-level list includes a first loop label for a first nested loop; and

presenting an icon adjacent the first loop label, the icon indicating whether a sub-list of one or more operations for the first nested loop is expanded or collapsed.

36-41. -41. (canceled)