Compiler-based critical section amendment for a multiprocessor environment

• US 20070006186A1
• Filed: 05/10/2005
• Published: 01/04/2007
• Est. Priority Date: 05/10/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Johnson, Erik, Goglin, Stephen
• Granted Patent: US 7,788,650 B2
• Time in Patent Office: Days
• US Class Current: 717/140
• CPC Class Codes: G06F 8/458 Synchronisation, e.g. post-wait, barriers, locks synchronisation among tasks G06F9/52

Abstract

Source code includes a directive to indicate data structures of related data to a compiler. The compiler associates the related data to the same one of multiple processors in a multiprocessor environment. The compiler searches the source code for locks associated with the related data, and generates executable code that is modified with respect to locks written in the source code. The compiler may replace or remove locks written in the source code to protect access to the related data, resulting in an executable program that does not include the locks.

Claims

1. A method comprising:

identifying data structures in source code that reference multiple instances of related data for an application in a multiprocessor, cache coherent system;

searching the source code to identify a synchronization command referencing the related data; and

compiling the source code to generate an executable program that excludes the identified synchronization command for the related data.

2. A method according to claim 1, wherein identifying the data structures comprises providing a language extension for a programming language used to develop the source code to indicate the related data.

3. A method according to claim 2, wherein identifying the data structures further comprises:

searching the source code for the language extension; and

indicating the language extension to a compiler to compile the source code.

4. A method according to claim 2, wherein providing the language extension comprises providing a pragma directive to indicate the related data.

5. A method according to claim 1, wherein the related data comprises data flows in a networking environment.

6. A method according to claim 1, wherein the related data comprises data associated with a matrix calculation.

7. A method according to claim 1, wherein searching the source code to identify the synchronization command comprises searching the source code to identify a critical section that locks the data for a particular processor of the multiple processors for a series of operations.

8. A method according to claim 1, wherein compiling the source code to generate the executable program that excludes the identified synchronization command further comprises excluding the synchronization command from an intermediate representation of the code in compiling the source code to the executable.

9. A method according to claim 8, wherein compiling the source code to generate the executable program that excludes the identified synchronization command further comprises replacing an inter-processor synchronization command with an intra-processor synchronization command for an implementation in a multi-threading processor.

10. An article of manufacture comprising a machine-accessible medium having content to provide instructions to result in an electronic device performing operations including:

identifying a data structure in source code indicated by a pragma directive, the data structure to represent separate a data flow for a multiprocessor, cache coherent system;

locating a critical section in the source code related to the identified data flow; and

compiling the source code to remove the located critical section and generate binary code from the source code, the binary code excluding the removed critical section.

11. An article of manufacture according to claim 10, wherein compiling to remove the located critical section comprises removing an inter-processor lock on the data structure.

12. An article of manufacture according to claim 11, wherein compiling the source code to remove the located critical section further comprises replacing the inter-processor lock with an inter-thread synchronization to lock the data structure for one of multiple threads in a multi-threading processor.

13. An article of manufacture according to claim 10, wherein the multiprocessor, cache coherent system supports receive-side scaling.

15. A system according to claim 13, wherein pre-processing the source code to mark the data structure further comprises searching the source code to determine whether a pragma statement in the source code identifies a data structure.

16. A system according to claim 13, wherein to locate the lock in the source code that references the related data comprises to determine that the lock is unnecessary because the related data would be pinned to a single processor without the lock.

14. A system comprising:

an article of manufacture comprising a machine-accessible medium having content to provide instructions to result in an electronic device performing operations including pre-processing source code to mark a data structure in source code indicated by a pre-processing directive to identify related data for a multiprocessor, cache coherent system, and to locate a lock in the source code that references the related data, and compiling the source code to generate an executable that lacks the lock;

an interface to receive the article of manufacture and access the content on the machine-accessible medium; and

a dynamic random access memory (DRAM) coupled to the interface to receive the accessed content from the interface and store the instructions for performing the operations.

17. An apparatus comprising:

a memory having data to define operations including identifying a data flow in source code marked by a programming language extension, the source code for an application for a multiprocessor, cache coherent system, searching the source code to identify a cache line lock for the data flow, and compiling the source code to generate an executable program that excludes the identified cache line lock; and

a processor coupled to the memory to execute the defined operations.

18. An apparatus according to claim 17, the multiprocessor, cache coherent system to support receive-side scaling.

19. An apparatus according to claim 17, wherein the programming language extension comprises a directive identifying the data flow to a compiler.

20. An apparatus according to claim 17, the memory further having data to identify an operation of refraining from passing cache coherency traffic for the cache line associated with the identified and excluded cache line lock.