Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer

• US 20070007508A1
• Filed: 07/13/2006
• Published: 01/11/2007
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Mears, Robert, A. Kreps, Scott
• Granted Patent: US 7,612,366 B2
• Time in Patent Office: Days
• US Class Current: 257/18
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Claims

1. A semiconductor device comprising:

a stress layer; and

a strained superlattice layer above said stress layer and comprising a plurality of stacked groups of layers;

each group of layers of said strained superlattice layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

2. The semiconductor device of claim 1 wherein said stress layer comprises a graded semiconductor layer.

3. The semiconductor device of claim 2 wherein said graded semiconductor layer is graded in a vertical direction;

and wherein said strained superlattice is vertically stacked on said graded semiconductor layer.

4. The semiconductor device of claim 2 further comprising a substantially ungraded semiconductor layer positioned between said graded semiconductor layer and said strained superlattice layer.

5. The semiconductor device of claim 2 wherein said graded semiconductor layer comprises graded silicon germanium.

6. The semiconductor device of claim 1 wherein said stress layer comprises a plurality of strain inducing pillars.

7. The semiconductor device of claim 1 further comprising an insulating layer positioned between said stress layer and said strained superlattice layer.

8. The semiconductor device of claim 1 further comprising regions for causing transport of charge carriers through said strained superlattice layer in a parallel direction relative to the stacked groups of layers.

9. The semiconductor device of claim 1 further comprising a semiconductor substrate adjacent said stress layer on a side thereof opposite said strained superlattice layer.

10. The semiconductor device of claim 1 wherein said strained superlattice layer has a compressive strain.

11. The semiconductor device of claim 1 wherein said strained superlattice layer has a tensile strain.

12. The semiconductor device of claim 1 wherein said strained superlattice layer has a common energy band structure therein.

13. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

14. The semiconductor device of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

15. The semiconductor device of claim 1 wherein each non-semiconductor monolayer comprises oxygen.

16. The semiconductor device of claim 1 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

17. The semiconductor device of claim 1 wherein adjacent base semiconductor portions are chemically bound together.

18. The semiconductor device of claim 1 wherein each non-semiconductor monolayer is a single monolayer thick.

19. The semiconductor device of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

20. The semiconductor device of claim 1 wherein said strained superlattice layer further has a substantially direct energy bandgap.

21. The semiconductor device of claim 1 wherein said strained superlattice layer further comprises a base semiconductor cap layer on an uppermost group of layers.

22. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.

23. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

24. A semiconductor device comprising:

a stress layer comprising a semiconductor graded in a vertical direction; and

a strained superlattice layer comprising a plurality of groups of layers vertically stacked on said graded semiconductor layer;

each group of layers of said strained superlattice layer comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

25. The semiconductor device of claim 24 further comprising a substantially ungraded semiconductor layer positioned between said stress layer and said strained superlattice layer.

26. The semiconductor device of claim 24 wherein said stress layer comprises graded silicon germanium.

27. The semiconductor device of claim 24 wherein said stress layer comprises a plurality of strain inducing pillars.

28. The semiconductor device of claim 24 further comprising an insulating layer positioned between said stress layers and said strained superlattice layer.

29. The semiconductor device of claim 24 further comprising regions for causing transport of charge carriers through said strained superlattice layer in a parallel direction relative to the stacked groups of layers.

30. The semiconductor device of claim 24 further comprising a semiconductor substrate adjacent said stress layer on a side thereof opposite said strained superlattice layer.

31. The semiconductor device of claim 24 wherein adjacent base semiconductor portions are chemically bound together.

32. A semiconductor device comprising:

a stress layer; and

a strained layer above said stress layer and comprising a plurality of base semiconductor portions and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

33. The semiconductor device of claim 32 wherein said stress layer comprises a graded semiconductor layer.

34. The semiconductor device of claim 33 wherein said graded semiconductor layer is graded in a vertical direction;

and wherein said strained layer is vertically stacked on said graded semiconductor layer.

35. The semiconductor device of claim 33 further comprising a substantially ungraded semiconductor layer positioned between said graded semiconductor layer and said strained layer.

36. The semiconductor device of claim 33 wherein said graded semiconductor layer comprises graded silicon germanium.

37. The semiconductor device of claim 32 wherein said stress layer comprises a plurality of strain inducing pillars.

38. The semiconductor device of claim 32 further comprising an insulating layer positioned between said stress layer and said strained layer.

39. The semiconductor device of claim 32 wherein adjacent base semiconductor portions are chemically bound together.