Semiconductor device and test method of semiconductor device

• US 20070007521A1
• Filed: 03/23/2006
• Published: 01/11/2007
• Est. Priority Date: 03/25/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshimatsu, Takanori
• Granted Patent: US 7,660,257 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

There is provided a semiconductor device comprising, a function unit portion including a circuit element, rank data presenting results of a rank-classification test on the circuit element, the rank-classification test being performed on the basis of a plurality of test criteria on wafer state, a non-volatile memory portion in which the rank data are stored, and a control portion reading out the rank data from the non-volatile memory portion, the control portion being used in a product test after packaging.

Claims

1. A semiconductor device, comprising:

a function unit portion including a circuit element;

a non-volatile memory portion in which rank data are stored, the rank data presenting results of a rank-classification test on the circuit element, the rank-classification test on the circuit element being performed on the basis of a plurality of test criteria on wafer state; and

a control portion reading out the rank data from the non-volatile memory portion, the control portion being used in a product test after packaging.

2. The semiconductor device according to claim 1, wherein the circuit element is a DRAM.

3. The semiconductor device according to claim 1, further comprising:

a logic circuit being included in the function unit portion.

4. The semiconductor device according to claim 1, wherein the non-volatile memory portion is a fuse or a non-volatile memory.

5. The semiconductor device according to claim 1, wherein the control portion is composed of a proper circuit portion.

6. The semiconductor device according to claim 1, wherein the control portion is included in the function unit portion.

7. A test method of a semiconductor device, comprising:

performing a rank-classification test on a circuit element included in a chip portion on wafer state on the basis of a plurality of test criteria; and

writing results of the rank-classification test as rank data into the non-volatile memory portion so that the rank data are stored in the non-volatile memory portion.

8. The test method according to claim 7, further comprising:

reading out the rank data from the non-volatile memory portion in the chip packaged after the writing the results of the rank-classification test as the rank data; and

performing a product test using the test criteria on the basis of the rank data, each one of the test criteria having the different rank.

9. The test method according to claim 7, wherein the rank data includes the results of the rank-classification test, the rank-classification test being performed corresponding to a plurality of test items.

10. The test method according to claim 8, further comprising:

sorting a chip on the basis of the rank data by combination of the plurality of test items after the reading out the rank data from the non-volatile memory portion in the chip packaged; and

performing a product test on the chip by using the test criteria corresponding to the rank data.

11. The test method according to claim 8, wherein the circuit element is a DRAM.

12. The test method according to claim 11, wherein the rank-classification test includes access time of the DRAM.

13. The test method according to claim 11, wherein the rank-classification test includes pause time of the DRAM.

14. The test method according to claim 7, wherein the rank-classification test includes a plurality of items.

15. The test method according to claim 7, wherein the non-volatile memory portion is a fuse or a non-volatile memory.

16. The test method according to claim 7, further comprising:

sorting the chip packaged by using the rank data after the writing the results of the rank-classification test as the rank data; and

performing a product test on the basis of the sorting by using test criteria of user requirement specifications.

17. The test method according to claim 16, wherein the user requirement specifications are constituted by a combination of a plurality of different ranks.