Semiconductor device with a buried gate and method of forming the same

• US 20070007571A1
• Filed: 07/06/2005
• Published: 01/11/2007
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hierlemann, Matthias, Lindsay, Richard
• Granted Patent: US 8,338,887 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 : with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Claims

1. A semiconductor device having a buried gate transistor, the semiconductor device comprising:

a semiconductor body that includes an active region surrounded by a trench isolation region;

a recess in a surface of the active region and in the trench isolation region;

a dielectric layer lining the recess; and

an electrode material filling the recess.

2. The semiconductor device of claim 1, wherein the dielectric layer is formed by a conformal deposition on both a bottom and sidewalls of the recess.

3. The semiconductor device of claim 1, wherein the electrode material has a substantially uniform thickness within the active region and within the trench isolation region.

4. The semiconductor device of claim 1, wherein the electrode material comprises a material selected from the group consisting of polysilicon, a metal, and combinations thereof.

5. The semiconductor device of claim 1, wherein the dielectric layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and nitrided compounds thereof.

6. The semiconductor device of claim 1, further comprising a second active region separated from the first active region by the trench isolation region, wherein the recess extends from the first active region across the trench isolation region and to the second active region.

7. The semiconductor device of claim 6, further comprising an n-channel transistor formed in the first active region and a p-channel transistor formed in the second active region, wherein the electrode material serves as a gate electrode for both the n-channel transistor and the p-channel transistor.

8. The semiconductor device of claim 1, wherein the device comprises a dynamic random access memory cell, wherein gate electrode material is electrically coupled to a word line, the device further comprising a capacitor coupled the active region of the semiconductor body.

9. The semiconductor device of claim 8, wherein the capacitor comprises a stack capacitor.

10. A buried gate transistor device comprising:

a semiconductor body including an active region, the active region surrounded by an isolation region;

a recess disposed in the active region;

a dielectric layer lining sidewalls and a bottom surface of the recess, the dielectric layer having a minimum thickness;

a gate electrode conductor filling the recess such that the dielectric layer is disposed between the gate electrode conductor and semiconductor material of the active region;

a first source/drain region disposed within the active region adjacent at least an upper portion of a first sidewall of the recess, the first source/drain region being heavily doped to a first conductivity type, wherein the first source/drain region abuts the dielectric layer at a point wherein the dielectric layer is at the minimum thickness and a first source/drain dopant concentration is at or close to its highest level;

a second source/drain region disposed within the active region adjacent at least an upper portion of a second sidewall of the recess, the second source/drain region being heavily doped to the first conductivity type, the second source/drain region being spaced from the first source/drain region by the recess, wherein the first source/drain region abuts the dielectric layer at a point wherein the dielectric layer is at the minimum thickness and a second source/drain dopant concentration is at or close to its highest level; and

a channel region disposed within the active region at least beneath the bottom surface of the recess, the channel region being lightly doped to a second conductivity type that is opposite the first conductivity type.

11. The device of claim 10, wherein the recess extends through portions of the isolation region adjacent the active region.

12. The device of claim 10, wherein the dielectric layer has a substantially uniform thickness along the sidewall and bottom surfaces of the recess.

13. The device of claim 10, wherein the dielectric layer comprises a high dielectric constant material.

14. A buried gate transistor device comprising:

an active area of semiconductor material, the active area having an upper surface;

a first source/drain region disposed in the active area;

a second source/drain region disposed in the active area;

a gate electrode disposed between the first source/drain region and the second source/drain region, a first portion the gate electrode recessed within the semiconductor material of the active area and a second portion of the gate electrode extending beyond the upper surface of the active area, the second portion of the gate electrode having sidewalls;

a gate dielectric disposed between the gate electrode and the semiconductor material of the active area;

sidewall spacers disposed along the sidewalls of the gate electrode; and

silicide regions formed in the first and second source/drain regions, the silicide regions being laterally spaced from the gate electrode by the sidewall spacers.

15. The device of claim 14, wherein the silicide region comprises cobalt silicide regions.

16. The device of claim 14, wherein the gate electrode comprises a semiconductor material, the device further comprising a silicide region along an upper portion of the gate electrode.

17. The device of claim 14, wherein the active area is surrounded by an isolation region, the gate electrode extending through a trench in the isolation region.

18. The device of claim 14, further comprising a channel region within the active area beneath the gate electrode, wherein the first source/drain meets the channel region at a location adjacent the dielectric layer where the dielectric layer is at its thinnest point.

19. A method of making a semiconductor device, the method comprising:

providing a semiconductor body;

forming a recess in a surface of the semiconductor body;

forming a dielectric liner in the recess;

forming a gate electrode in the recess; and

after forming the buried gate, forming first and second highly doped source/drain regions in the semiconductor body, the first and second highly doped source/drain regions being laterally spaced by the gate electrode.

20. The method of claim 19, wherein forming the recess comprises lithographically patterning and etching a recess between about 5 nm and about 200 nm.

21. The method of claim 19, wherein forming a dielectric liner comprises thermally growing an oxide layer.

22. The method of claim 19, wherein forming a dielectric liner comprises depositing a high-k material.

23. The method of claim 19, wherein forming a gate electrode comprises forming a buried gate electrode that extends out of an active region, the method further comprising:

forming sidewall spacers along sidewalls of the gate electrode;

forming a silicide over the first and second source/drain regions, the silicide being laterally spaced from the gate electrode by the sidewall spacers.

24. The method of claim 19, further comprising performing a halo implant after forming the recess.

25. The method of claim 24, where the halo implant is performed using a tilt angle implant that uses the Si recess and hard mask geometry to shadow, and thereby localize, the implant solely at edges of a channel while avoiding implant in bulk of the channel.

26. The method of claim 19, further comprising forming a first recessed source/drain region over the first source/drain region and a second raised source/drain region over the second source/drain region.

27. A method of making a semiconductor device, the method comprising:

providing a semiconductor body with a first active region, a second active region, and an isolation region between the first active region and the second active region;

forming a recess in a surface of the semiconductor body, the recess extending across the first active region, the isolation region and the second active region;

forming a gate dielectric within the recess;

forming a gate electrode in the recess; and

forming first and second source/drain regions in the first active area and third and fourth source/drain regions in the second active regions, the first source/drain region being spaced from the second source/drain region by the gate electrode and third source/drain region being spaced from the fourth source/drain region by the gate electrode.

28. The method of claim 27, wherein the source/drain regions are formed after forming the gate electrode.

29. The method of claim 27, further comprising doping a channel region in the first and second active regions, before forming the gate electrode.

30. The method of claim 27, wherein the first active region comprises an n-doped semiconductor and the second active region comprises a p-doped semiconductor.

31. The method of claim 27, further comprising:

electrically coupling the first source/drain region to the third source/drain region;

electrically coupling the second source/drain region to a first supply voltage node; and

electrically coupling the fourth source/drain region to a second supply voltage node.