Semiconductor device with a buried gate and method of forming the same
First Claim
1. A semiconductor device having a buried gate transistor, the semiconductor device comprising:
- a semiconductor body that includes an active region surrounded by a trench isolation region;
a recess in a surface of the active region and in the trench isolation region;
a dielectric layer lining the recess; and
an electrode material filling the recess.
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Accused Products
Abstract
An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.
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Citations
31 Claims
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1. A semiconductor device having a buried gate transistor, the semiconductor device comprising:
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a semiconductor body that includes an active region surrounded by a trench isolation region;
a recess in a surface of the active region and in the trench isolation region;
a dielectric layer lining the recess; and
an electrode material filling the recess. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A buried gate transistor device comprising:
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a semiconductor body including an active region, the active region surrounded by an isolation region;
a recess disposed in the active region;
a dielectric layer lining sidewalls and a bottom surface of the recess, the dielectric layer having a minimum thickness;
a gate electrode conductor filling the recess such that the dielectric layer is disposed between the gate electrode conductor and semiconductor material of the active region;
a first source/drain region disposed within the active region adjacent at least an upper portion of a first sidewall of the recess, the first source/drain region being heavily doped to a first conductivity type, wherein the first source/drain region abuts the dielectric layer at a point wherein the dielectric layer is at the minimum thickness and a first source/drain dopant concentration is at or close to its highest level;
a second source/drain region disposed within the active region adjacent at least an upper portion of a second sidewall of the recess, the second source/drain region being heavily doped to the first conductivity type, the second source/drain region being spaced from the first source/drain region by the recess, wherein the first source/drain region abuts the dielectric layer at a point wherein the dielectric layer is at the minimum thickness and a second source/drain dopant concentration is at or close to its highest level; and
a channel region disposed within the active region at least beneath the bottom surface of the recess, the channel region being lightly doped to a second conductivity type that is opposite the first conductivity type. - View Dependent Claims (11, 12, 13)
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14. A buried gate transistor device comprising:
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an active area of semiconductor material, the active area having an upper surface;
a first source/drain region disposed in the active area;
a second source/drain region disposed in the active area;
a gate electrode disposed between the first source/drain region and the second source/drain region, a first portion the gate electrode recessed within the semiconductor material of the active area and a second portion of the gate electrode extending beyond the upper surface of the active area, the second portion of the gate electrode having sidewalls;
a gate dielectric disposed between the gate electrode and the semiconductor material of the active area;
sidewall spacers disposed along the sidewalls of the gate electrode; and
silicide regions formed in the first and second source/drain regions, the silicide regions being laterally spaced from the gate electrode by the sidewall spacers. - View Dependent Claims (15, 16, 17, 18)
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19. A method of making a semiconductor device, the method comprising:
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providing a semiconductor body;
forming a recess in a surface of the semiconductor body;
forming a dielectric liner in the recess;
forming a gate electrode in the recess; and
after forming the buried gate, forming first and second highly doped source/drain regions in the semiconductor body, the first and second highly doped source/drain regions being laterally spaced by the gate electrode. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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27. A method of making a semiconductor device, the method comprising:
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providing a semiconductor body with a first active region, a second active region, and an isolation region between the first active region and the second active region;
forming a recess in a surface of the semiconductor body, the recess extending across the first active region, the isolation region and the second active region;
forming a gate dielectric within the recess;
forming a gate electrode in the recess; and
forming first and second source/drain regions in the first active area and third and fourth source/drain regions in the second active regions, the first source/drain region being spaced from the second source/drain region by the gate electrode and third source/drain region being spaced from the fourth source/drain region by the gate electrode. - View Dependent Claims (28, 29, 30, 31)
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Specification