Circuit for detecting difference in capacitance
First Claim
1. A circuit for detecting a difference in capacitance between a first capacitor and a second capacitor provided in a sensor, comprising:
- a first oscillator configured to generate a first oscillating signal having frequency responsive to the first capacitor;
a second oscillator configured to generate a second oscillating signal having frequency responsive to the second capacitor;
a first counter coupled to said first oscillator to output a first count responsive to said first oscillating signal;
a second counter coupled to said second oscillator to output a second count responsive to said second oscillating signal; and
an operation circuit coupled to said first counter and said second counter to output a signal indicative of the difference in capacitance in response to the first count and the second count.
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Accused Products
Abstract
A circuit for detecting a difference in capacitance between a first capacitor and a second capacitor provided in a sensor includes an oscillator configured to generate an oscillating signal, a phase comparator coupled to the oscillator to output a signal responsive to a phase difference between the oscillating signal delayed by the first capacitor and the oscillating signal delayed by the second capacitor, an integration circuit coupled to the phase comparator to output an integrated signal made by integrating the signal responsive to the phase difference over a time period equal to a predetermined number of cycles of the oscillating signal, and a sample-and-hold circuit coupled to the integration circuit to output a signal made by sampling and holding the integrated signal at substantially an end of the time period.
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Citations
6 Claims
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1. A circuit for detecting a difference in capacitance between a first capacitor and a second capacitor provided in a sensor, comprising:
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a first oscillator configured to generate a first oscillating signal having frequency responsive to the first capacitor;
a second oscillator configured to generate a second oscillating signal having frequency responsive to the second capacitor;
a first counter coupled to said first oscillator to output a first count responsive to said first oscillating signal;
a second counter coupled to said second oscillator to output a second count responsive to said second oscillating signal; and
an operation circuit coupled to said first counter and said second counter to output a signal indicative of the difference in capacitance in response to the first count and the second count. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification