High-speed differential receiver

• US 20070008002A1
• Filed: 06/30/2005
• Published: 01/11/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lawson, William, Williams, Devon
• Granted Patent: US 7,385,424 B2
• Time in Patent Office: Days
• US Class Current: 326/80
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and differential level shifter operates at the high voltage domain. The differential level shifter receives amplified differential signals from the common mode differential amplifier and provides voltage level shifted differential signals applied to a biased differential amplifier operating at the low voltage domain.

Claims

1. A high-speed differential receiver used between a high voltage domain and a low voltage domain;

said high-speed differential receiver comprising;

a common mode differential amplifier receiving differential input signals and providing amplified differential output signals;

a differential level shifter coupled to said common mode differential amplifier;

said common mode differential amplifier and differential level shifter operating at the high voltage domain;

said differential level shifter receiving said amplified differential output signals from the common mode differential amplifier and providing voltage level shifted differential signals;

a biased differential amplifier operating at the low voltage domain and coupled to said differential level shifter receiving said voltage level shifted differential signals.

2. A high-speed differential receiver as recited in claim 1 wherein said common mode differential amplifier is a wide common mode differential amplifier and the high voltage domain includes a range between 2.3 Volts and 2.7 Volts.

3. A high-speed differential receiver as recited in claim 1 wherein said differential level shifter includes a pair of P-channel field effect transistors (PFETs) connected to the high voltage domain.

4. A high-speed differential receiver as recited in claim 3 wherein each said PFET respectively receives a gate input of a respective one of said amplified differential output signals from said common mode differential amplifier.

5. A high-speed differential receiver as recited in claim 4 wherein each said PFET is series connected with a respective N-channel field effect transistor (NFET) between the high voltage supply and ground.

6. A high-speed differential receiver as recited in claim 5 wherein a gate of each said NFET is cross connected to a common drain connection of the other series connect PFET and NFET.

7. A high-speed differential receiver as recited in claim 5 wherein said differential level shifter includes a pair of N-channel field effect transistors (NFETs) connected in parallel with each said NFET.

8. A high-speed differential receiver as recited in claim 2 wherein said biased differential amplifier operating at the low voltage domain includes a range between 0.8 Volts and 1.3 Volts.

9. A high-speed differential receiver as recited in claim 2 wherein said biased differential amplifier receives an enable signal for providing a biased output signal.

10. A high-speed differential receiver as recited in claim 1 includes a NAND INVERT output stage coupled to said biased differential amplifier.

11. A high-speed differential receiver as recited in claim 1 includes a terminator connected between a pair of inputs of said common mode differential amplifier receiving said differential input signals.

12. A high-speed differential receiver used between a high voltage domain and a low voltage domain;

said high-speed differential receiver comprising;

a wide common mode differential amplifier receiving differential input signals and providing amplified differential output signals;

a differential level shifter coupled to said common mode differential amplifier for providing voltage level shifted differential signals;

said common mode differential amplifier and differential level shifter operating at the high voltage domain;

said differential level shifter including a pair of P-channel field effect transistors (PFETs), each said PFET respectively receives a gate input of a respective one of said amplified differential output signals, each said PFET connected in series with a respective N-channel field effect transistor (NFET) between the high voltage supply and ground, and a gate of each said NFET is cross connected to a common drain connection of the other series connect PFET and NFET;

a biased differential amplifier operating at the low voltage domain and coupled to said differential level shifter receiving said voltage level shifted differential signals.

13. A high-speed differential receiver as recited in claim 12 wherein said differential level shifter includes a pair of N-channel field effect transistors (NFETs) connected in parallel with each said NFET.

14. A high-speed differential receiver as recited in claim 12 wherein the high voltage domain includes a range between 2.3 Volts and 2.7 Volts.

15. A high-speed differential receiver as recited in claim 12 wherein the low voltage domain includes a range between 0.8 Volts and 1.3 Volts.

16. A high-speed differential receiver as recited in claim 12 includes a NAND INVERT output stage coupled to said biased differential amplifier.

17. A high-speed differential receiver as recited in claim 12 includes a terminator connected between a pair of inputs of said common mode differential amplifier receiving said differential input signals.