High voltage integrated circuit driver with a high voltage PMOS bootstrap diode emulator

• US 20070008010A1
• Filed: 09/08/2006
• Published: 01/11/2007
• Est. Priority Date: 07/21/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Bryson, Stephen
• Granted Patent: US 7,538,583 B2
• Time in Patent Office: Days
• US Class Current: 326/88
• CPC Class Codes: H03F 2200/31 the switching power stage comprising circuitry for emulating the behaviour of a bootstrap diode
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 19/01735 by bootstrapping, i.e. by positive feed-back

Abstract

A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is embedded in an N-isolation layer and is integrated with the driver cells. A bootstrap control circuit, for controlling the HVPMOS, includes a high voltage level shift stage, which can also be embedded in an N-isolation layer. The circuit driver is operated by switching the high side drive signal from high to low, the low side drive signal from low to high with a first delay, and a bootstrap control signal from high to low with an additional second delay. Also, the bootstrap capacitor is first charged by switching on the HVPMOS, and then it energizes the high side driver cell.

Claims

1. A high voltage circuit driver, comprising:

a high side driver cell, operable to drive a gate of a high side power MOSFET;

a low side driver cell, operable to drive a gate of a low side power MOSFET;

a bootstrap circuit, coupled between an output node and a supply-voltage terminal of the high side driver cell;

a high voltage PMOS transistor, coupled between a first voltage source terminal and the bootstrap circuit, wherein the high voltage PMOS transistor is embedded in an N-isolation layer and is integrated with the driver cells;

a bootstrap control circuit, coupled to the high voltage PMOS transistor; and

a high side driver control circuit and a low side driver control circuit, coupled to the high side driver cell and the low side driver cell, respectively.

2. The circuit driver of claim 1, wherein:

the high side driver cell is coupled to the gate of the high side power MOSFET;

the high side power MOSFET is configured to be coupled between a power supply and the output node;

the low side driver cell is coupled to the gate of the low side power MOSFET; and

the low side power MOSFET is coupled between the output node and a ground.

3. The circuit driver of claim 1, wherein:

the high voltage PMOS transistor is configured as a diode emulator.

4. The circuit driver of claim 1, wherein:

the source and the body of the high voltage PMOS transistor are electrically coupled.

5. The circuit driver of claim 1, wherein:

the body of the high voltage PMOS transistor is not grounded.

6. The circuit driver of claim 1, wherein:

the high voltage PMOS transistor is configured to be operated at a floating voltage.

7. The circuit driver of claim 1, wherein the high voltage PMOS transistor comprises:

an N-buried layer, partially overlying the N-isolation layer;

an N-well, partially overlying the N-buried layer;

a source, formed on the N-well;

a P-well, partially overlying the N-isolation layer, formed in the proximity of the N-well;

a drain, formed on the P-well; and

oxide layers.

8. The circuit driver of claim 1, wherein:

the circuit driver does not contain circuit elements to control a voltage between the body and one of the source and the drain of the high voltage PMOS transistor.

9. The circuit driver of claim 1, wherein:

a level shifting stage of the bootstrap control circuit is embedded in an N-isolation well.

10. The circuit driver of claim 1, wherein the bootstrap circuit comprises a bootstrap capacitor.

11. The circuit driver of claim 1, wherein the power supply is capable of providing a voltage between 0V and 30V.

12. The circuit driver of claim 1, wherein the circuit driver is configured to be part of a DC-to-DC converter.

13. The circuit driver of claim 1, further comprising an inductor-capacitor filter circuit, coupled between the output node and a ground.

14. The circuit driver of claim 1, wherein:

at least two of the bootstrap control circuit, the high side driver control circuit, and the low side driver control circuit are integrated into a control circuit.

15. A controller of a high voltage driver,

the high voltage driver comprising:

a high side power MOSFET, configured to be coupled between a power supply and an output node;

a low side power MOSFET, coupled between the output node and a ground;

a high side driver cell, coupled to a gate of the high side power MOSFET;

a low side driver cell, coupled to a gate of the low side power MOSFET;

a bootstrap circuit, coupled between the output node and a supply-voltage terminal of the high side driver cell; and

a high voltage PMOS transistor, coupled between a first voltage source and the bootstrap circuit;

the controller comprising;

a comparator;

a delay element, coupled to the comparator;

logic circuitry, a first input of the logic circuitry coupled to the delay element; and

a high voltage level shift stage, the output of the logic circuitry coupled into the high voltage level shift stage, the output of the high voltage level shift stage coupled to the high voltage PMOS transistor;

wherein

the high voltage level shift stage is embedded in an N-isolation layer and is integrated with the driver cells.

16. The controller of claim 15, the logic circuitry comprising:

a NOR gate, a first input terminal of the NOR gate coupled to the delay element and a second input terminal of the NOR gate coupled to a logic input terminal through an inverter.

17. The controller of claim 16, further comprising:

a Set-Reset latch, a Set input terminal of the Set-Reset latch coupled to an output terminal of the NOR gate and a Reset input terminal of the latch coupled to the second input terminal of the NOR gate, an output terminal of the latch coupled to a gate of the high voltage PMOS transistor.

18. The controller of 15, wherein the high voltage PMOS transistor is embedded into an N-isolation layer.

19. The method of operating a high voltage driver, the method comprising:

switching a high side drive signal from high to low, applied to a high side driver cell of a converter;

switching a low side drive signal from low to high with a first delay, applied to a low side driver cell of the converter; and

switching a bootstrap control signal from high to low with a second delay, applied to a high voltage PMOS transistor, the PMOS transistor being embedded into an N-isolation layer and integrated with the driver cells, wherein;

the second delay is partially subsequent to the first delay.

20. The method of claim 19, the method further comprising:

controlling the high voltage driver to ensure that a high side power transistor, driven by the high side driver cell, and a low side power transistor, driven by the low side driver cell, are not switched on simultaneously.