Distributed power and clock management in a computerized system

• US 20070008011A1
• Filed: 06/29/2005
• Published: 01/11/2007
• Est. Priority Date: 06/29/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Thurston, Paulette
• Application Number:
  US11/170,770
• Publication Number:
  US 20070008011A1
• Time in Patent Office: Days
• US Class Current: 326/93
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer circuit includes a plurality of digital logic circuits, each having a locally regulated voltage supply and a clock. The clock and locally regulated voltage supply of each of the plurality of digital logic circuits are operable to vary under control of a common power controller. A synchronizer coupled to each of the plurality of digital logic circuits, and each synchronizer is operable to synchronize the exchange of data with at least one other digital logic circuit.

Claims

1. A computer circuit, comprising:

a plurality of digital logic circuits, each having a locally regulated voltage supply and a clock, the clock frequency of two or more local clocks and the voltage of two or more locally regulated voltage supplies adjustable under control of a common power controller; and

a synchronizer coupled to each of the plurality of digital logic circuits, each synchronizer operable to synchronize the exchange of data with at least one other digital logic circuit.

2. The computer circuit of claim 1, wherein the plurality of digital logic circuits are on the same integrated circuit.

3. The computer circuit of claim 1, wherein at least one of the plurality of digital logic circuits further comprises one or more registers operable to retain data while the digital logic circuit'"'"'s voltage is reduced such that the digital logic circuit is inoperable.

4. The computer circuit of claim 1, wherein at least two of the plurality of digital logic circuits are coupled via their respective synchronizers by a bus.

5. The computer circuit of claim 1, wherein the plurality of logic circuits comprise functional units within a processor.

6. The computer circuit of claim 5, wherein the processor is a multi-core processor.

7. The computer circuit of claim 1, wherein at least two of the plurality of logic circuits comprise peripheral device logic within a computerized system.

8. A method of managing a plurality of digital logic circuits in an electronic system, comprising:

controlling the voltage provided from voltage regulators local to each of the plurality of digital logic circuits;

controlling the frequency of a clock signal generated local to each of the plurality of digital logic circuits; and

synchronizing exchange of data between at least two of the plurality of digital logic circuits via a synchronizer in at least two of the plurality of digital logic circuits

9. The method of claim 8, wherein the plurality of digital logic circuits are on the same integrated circuit.

10. The method of claim 8, further comprising retaining logic circuit state data in registers powered sufficiently to retain their states for at least one of the plurality of digital logic circuits when in a reduced voltage mode such that the digital logic circuit is inoperable.

11. The method of claim 8, wherein at least two of the plurality of digital logic circuits are coupled via their respective synchronizers by a bus.

12. The method of claim 8, wherein the plurality of logic circuits comprise functional units within a processor.

13. The method of claim 12, wherein the processor is a multi-core processor.

14. The method of claim 8, wherein at least two of the plurality of logic circuits comprise peripheral device logic within a computerized system.

15. An electronic system, comprising:

a plurality of digital logic circuits, each having a locally regulated voltage supply and a clock;

a power controller operable to control the clock and regulated voltage supply local to each of the plurality of digital logic circuits;

a battery operable to power the plurality of digital logic circuits; and

a synchronizer coupled to each of the plurality of digital logic circuits, each synchronizer operable to synchronize the exchange of data with at least one other digital logic circuit.

16. The electronic system of claim 15, wherein the plurality of digital logic circuits are on the same integrated circuit.

17. The electronic system of claim 15, wherein at least one of the plurality of digital logic circuits further comprises one or more registers operable to retain data while the digital logic circuit'"'"'s voltage is reduced such that the digital logic circuit is inoperable.

18. The electronic system of claim 15, wherein at least two of the plurality of digital logic circuits are coupled via their respective synchronizers by a bus.

19. The electronic system of claim 15, wherein the plurality of logic circuits comprise functional units within a processor.

20. The electronic system of claim 19, wherein the processor is a multi-core processor.

21. The electronic system of claim 15, wherein at least two of the plurality of logic circuits comprise peripheral device logic within a computerized system.

22. The electronic system of claim 15, wherein the device comprises a cell phone, a personal digital assistant, a gaming system, or a portable computer.

23. A logic circuit, comprising:

a regulated voltage supply operable to provide a regulated voltage to the logic circuit;

a clock operable to provide a local clock signal to the logic circuit;

a power controller interface operable to receive a control signal for controlling the regulated voltage supply voltage and the clock frequency; and

a synchronizer interface operable to synchronize data exchange with at least one other digital logic circuit having separate clocks and regulated voltage supplies.

24. The logic circuit of claim 23, wherein the plurality of digital logic circuits are on the same integrated circuit.

25. The logic circuit of claim 23, wherein at least one of the plurality of digital logic circuits further comprises one or more registers operable to retain data while the digital logic circuit'"'"'s voltage is reduced such that the digital logic circuit is inoperable.

26. The logic circuit of claim 23, wherein at least two of the plurality of digital logic circuits are coupled via their respective synchronizers by a bus.

27. The logic circuit of claim 23, wherein the plurality of logic circuits comprise functional units within a processor.

28. The logic circuit of claim 27, wherein the processor is a multi-core processor.

29. The logic circuit of claim 23, wherein at least two of the plurality of logic circuits comprise peripheral device logic within a computerized system.