Scannable dynamic circuit latch
First Claim
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1. A dynamic circuit latch comprising:
- a domino component, for receiving a clock signal and an input signal, and for producing an output; and
a state component, coupled to said domino component, for retaining said output, wherein said domino component and said state component are configured to assume a tristate when induced by said clock signal, such that said output is held at said state component, and wherein said input signal cannot alter said output while so held.
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Abstract
A dynamic circuit latch, having the functionality of a domino circuit and a transparent latch, without the delay associated with the inclusion of a separate series latch element. Embodiments include a fast scannable footed Domino dyanmic latch. Also described is a fast scannable delay reset Domino dynamic latch. A fast scannable compound Domino dynamic latch is also described.
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Citations
27 Claims
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1. A dynamic circuit latch comprising:
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a domino component, for receiving a clock signal and an input signal, and for producing an output; and
a state component, coupled to said domino component, for retaining said output, wherein said domino component and said state component are configured to assume a tristate when induced by said clock signal, such that said output is held at said state component, and wherein said input signal cannot alter said output while so held. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A scannable latch circuit comprising:
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a domino circuit comprising a data input port for receiving an input data signal and a clock input port for receiving a clock input wherein said domino circuit is operable to generate an output signal over an output port; and
a scannable state circuit coupled to said output port, wherein said scannable state circuit, in a first clock mode, is operable to hold a signal state of said output port and, wherein further, signal transitions at said input port do not alter said signal state. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. A dynamic circuit latch, comprising:
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a domino component having a clock port to receive a clock signal and an input port to receive an input signal, wherein said domino component is operable in a first clock state to produce an output at an output port, and wherein said domino component is operable in a second clock state to prevent said input from affecting said output; and
a state component coupled to said output port, wherein said state component is operable in said first clock state to inhibit conduction through said state component, and wherein said state component is operable in a second clock state to hold said output. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification