Scannable dynamic circuit latch

• US 20070008012A1
• Filed: 06/30/2005
• Published: 01/11/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Kottapalli, Venkata, Masleid, Robert, Sousa, Jose
• Granted Patent: US 7,663,408 B2
• Time in Patent Office: Days
• US Class Current: 326/98
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

A dynamic circuit latch, having the functionality of a domino circuit and a transparent latch, without the delay associated with the inclusion of a separate series latch element. Embodiments include a fast scannable footed Domino dyanmic latch. Also described is a fast scannable delay reset Domino dynamic latch. A fast scannable compound Domino dynamic latch is also described.

Claims

1. A dynamic circuit latch comprising:

a domino component, for receiving a clock signal and an input signal, and for producing an output; and

a state component, coupled to said domino component, for retaining said output, wherein said domino component and said state component are configured to assume a tristate when induced by said clock signal, such that said output is held at said state component, and wherein said input signal cannot alter said output while so held.

2. The dynamic circuit latch of claim 1 free of the delay imposed by inclusion of a separate series latch circuit.

3. The dynamic circuit latch of claim 1, wherein said state component comprises:

a first tristate buffer; and

a second tristate buffer coupled to said first tristate buffer, wherein said first tristate buffer and said second tristate buffer are configured to function as an exposed, scannable latch when said domino component is in said tristate condition.

4. The dynamic circuit latch of claim 3, further comprising:

a slave latch assembly, coupled to said second tristate buffer, and configured to allow monitoring of said output.

5. The dynamic circuit latch of claim 1, wherein said domino component comprises:

a precharge component, for precharging said domino component;

a function component, coupled to said precharge component, for performing a function with said input signal and producing said output;

a keeper component, coupled to said precharge component, for holding said output from said function component; and

an output component, coupled to said precharge component, for holding said output.

6. The dynamic circuit latch of claim 5, wherein said domino component further comprises:

a foot component, coupled to said precharge component, for cutting off said input signal when induced by said clock signal.

7. The dynamic circuit latch of claim 1, wherein said domino component comprises:

a plurality of precharge components;

a plurality of function components, coupled to said plurality of precharge components, for performing a plurality of functions and producing a plurality of outputs;

a plurality of keeper components, coupled to said plurality of precharge components, for holding said plurality of outputs; and

an output component, coupled to said plurality of precharge components, for holding said output.

8. A scannable latch circuit comprising:

a domino circuit comprising a data input port for receiving an input data signal and a clock input port for receiving a clock input wherein said domino circuit is operable to generate an output signal over an output port; and

a scannable state circuit coupled to said output port, wherein said scannable state circuit, in a first clock mode, is operable to hold a signal state of said output port and, wherein further, signal transitions at said input port do not alter said signal state.

9. A scannable latch circuit as described in claim 8 wherein said scannable state circuit comprises a scan-in port and a scan-out port.

10. A scannable latch circuit as described in claim 9 wherein said scannable state circuit further comprises a scan clock input.

11. A scannable latch circuit as described in claim 10 wherein said domino circuit comprises a footed domino circuit.

12. A scannable latch circuit as described in claim 10 wherein said domino circuit comprises a delay reset domino circuit.

13. A scannable latch circuit as described in claim 10 wherein said domino circuit comprises a compound domino circuit.

14. A scannable latch circuit as described in claim 8 wherein said domino circuit further comprises:

a precharge subcircuit;

a keeper subcircuit coupled to said precharge subcircuit; and

an output buffer subcircuit coupled to said keeper subcircuit and coupled to said precharge subcircuit wherein said output buffer subcircuit is for generating said output signal.

15. A scannable latch circuit as described in claim 14 wherein said scannable state circuit further comprises:

a first tri-state buffer circuit coupled to a scan-in port and coupled to said output port;

a second tri-state buffer circuit coupled to said first tri-state buffer circuit and coupled to said output port; and

a scan-out read circuit coupled to said second tri-state buffer circuit and coupled to a scan-out port.

16. A scannable latch circuit as described in claim 8 wherein said scannable state circuit further comprises:

a first tri-state buffer circuit coupled to a scan-in port;

a second tri-state buffer circuit coupled to said first tri-state buffer circuit; and

a scan-out read circuit coupled to said second tri-state buffer circuit and coupled to a scan-out port.

17. A dynamic circuit latch, comprising:

a domino component having a clock port to receive a clock signal and an input port to receive an input signal, wherein said domino component is operable in a first clock state to produce an output at an output port, and wherein said domino component is operable in a second clock state to prevent said input from affecting said output; and

a state component coupled to said output port, wherein said state component is operable in said first clock state to inhibit conduction through said state component, and wherein said state component is operable in a second clock state to hold said output.

18. The dynamic circuit latch of claim 17 wherein said domino component comprises a footed domino circuit.

19. The dynamic circuit latch of claim 17 wherein said domino circuit comprises a delay reset domino circuit.

20. The dynamic circuit latch of claim 17 wherein said domino circuit comprises a compound domino circuit.

21. The dynamic circuit latch of claim 20 wherein said compound domino circuit comprises a footed compound domino circuit.

22. The dynamic circuit latch of claim 20 wherein said compound domino circuit comprises a delay resetcompound domino circuit.

23. The dynamic circuit latch of claim 17 wherein said state element comprises:

a scan-in read circuit coupled to a scan-in port and coupled to said output port; and

a scan-out read circuit coupled to said scan-in read circuit and coupled to a scan-out port for outputting a held value.

24. The dynamic circuit latch of claim 21 wherein said state element further comprises:

a first tristate buffer circuit coupled to said scan-in port and coupled to a scan-clock input port; and

a second tristate buffer circuit coupled to said first tristate buffer and coupled to a functional clock input port.

25. The dynamic circuit latch of claim 24 wherein said state element further comprises:

a scan-out read circuit coupled to said second tristate buffer circuit and coupled to said scan-out port.

26. The dynamic circuit latch of claim 17 wherein said domino component further comprises:

a precharge subcircuit;

a keeper subcircuit coupled to said precharge subcircuit; and

an output buffer subcircuit coupled to said keeper subcircuit and coupled to said precharge subcircuit wherein said output buffer subcircuit is for generating said output signal.

27. The dynamic circuit latch of claim 26 wherein said state component further comprises:

a first tristate buffer circuit coupled to a scan-in port and coupled to said output port;

a second tristate buffer circuit coupled to said first tristate buffer circuit and coupled to said output port; and

a scan-out read circuit coupled to said second tristate buffer circuit and coupled to a scan-out port.