Serial camera interface

• US 20070008414A1
• Filed: 07/08/2005
• Published: 01/11/2007
• Est. Priority Date: 07/08/2005
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Rai, Barinder, Dyke, Phil
• Granted Patent: US 7,602,422 B2
• Time in Patent Office: Days
• US Class Current: 348/207.990
• CPC Class Codes: H04N 23/665 involving internal camera communication with the image sensor, e.g. synchronising or multiplexing SSIS control signals
• CPC Class Codes: H04N 5/222 Studio circuitry; Studio devices; Studio equipment cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00

Abstract

An interface for a graphics controller enabling communication with a camera module is provided. The interface includes a first port configured to receive serial image data from a camera module and a second port configured to receive a clock signal, wherein the clock signal is utilized to indicate both a horizontal synchronization and a vertical synchronization for frames of image data received from the camera module. An image capture device having the serial interface and methods for reducing a number of signals utilized for an interface receiving image data are also included.

Claims

1. An image capture device, comprising:

a camera module configured to capture image data;

a graphics controller, the graphics controller including,

counter/comparator logic for recognizing an end of a horizontal line of the image data; and

clock pause recognition logic configured to detect an interruption in a clock signal indicative of an end of a frame of the image data; and

first and second signal lines connecting the camera module and the graphics controller, wherein the first signal line serially transfers the image data from the camera module to the graphics controller and the second signal line communicates a clock signal between the camera module to the graphics controller.

2. The device of claim 1, wherein a maximum of two signal lines connect the camera module and the graphics controller.

3. The device of claim 1, wherein the camera module is one of a complimentary metal oxide semiconductor (CMOS) sensor or a charged coupled device (CCD).

4. The device of claim 1, further comprising:

a first register and a second register configured to store a value representing an image resolution size.

5. The device of claim 4, wherein the counter/comparator logic includes a counter configured to increment a counter value as each pixel data value is received and a comparator configured to compare the counter value the first register value to determine the end of the horizontal line of image data.

6. The device of claim 1, wherein the clock pause recognition logic is further configured to detect a resumption of a clock signal thereby indicating a start of a next frame of image data.

7. The device of claim 1, wherein the device is selected from the group consisting of a cellular phone, a personal digital assistant, a web tablet, and a pocket personal computer.

8. An interface for a graphics controller enabling communication with a camera module, comprising:

a first port configured to receive serial image data from a camera module;

a second port configured to receive a clock signal, wherein the clock signal is utilized to indicate both a horizontal synchronization and a vertical synchronization for frames of image data received from the camera module.

9. The interface of claim 8, further comprising:

counter/comparator logic for recognizing an end of a horizontal line of one of the frames of image data; and

clock pause recognition logic configured to detect an interruption in the clock signal indicative of an end of one of the frames of image data.

10. The interface of claim 8, wherein the interface is incorporated into a consumer electronic device having camera functionality.

11. The interface of claim 8, wherein the serial image data in a format selected from the group consisting of YUV422 format, YUV420 format, RGB565 format, and Bayer data format.

12. A method for signaling a start and end of frame and line data for a serial interface having a maximum of two signal lines, comprising method operations of:

receiving image data over a first line;

receiving a clock signal associated with the data over a second line;

while receiving the image data, the method includes,

counting a number of clock cycles;

comparing the number of clock cycles to a value representing a number of pixels defining a horizontal line within the frame data;

continuing the counting and the comparing until the number of clock cycles matches the value;

when the number of clock cycles matches the value, the method includes,

identifying the end of the line data;

resetting a count representing the number of clock cycles;

counting the number of clock cycles;

comparing the number of clock cycles to a value representing a non-display period between horizontal lines within the frame data; and

when the number of clock cycles matches the value representing the non-display period, the method includes,

repeating the above method operations for successive line data.

13. The method of claim 12, further comprising:

identifying a pause in toggling of the clock signal; and

signifying the end of the frame of image data in response to the pause.

14. The method of claim 12 further comprising:

detecting a resumption in toggling of the clock signal after a break in the toggling of the clock cycle; and

signaling a start of a next frame of image data in response to the resumption.

15. The method of claim 12, wherein the method operation of comparing the number of clock cycles to a value representing a number of pixels defining a horizontal line within the frame data includes,

accessing a register storing the value.

16. The method of claim 12, wherein the image data received over the first line is in a serial format.

17. A method for reducing a number of signals utilized for an interface receiving image data, comprising method operations of:

receiving image data in a serial format over a first signal line;

receiving a clock signal over a second signal line; and

monitoring the clock signal to identify both transitions between frames of the image data and transitions between horizontal lines within a frame of the image data.

18. The method of claim 17, wherein the method operation of monitoring the clock signal to identify both transitions between frames of the image data and transitions between horizontal lines within a frame of the image data includes,

detecting a break in the clock signal;

issuing an end of frame signal in response to the break;

detecting a resumption of the clock signal; and

issuing a beginning of frame signal in response to the resumption.

19. The method of claim 17, wherein the method operation of monitoring the clock signal to identify both transitions between frames of the image data and transitions between horizontal lines within a frame of the image data includes,

counting a number of clock cycles;

comparing the number of clock cycles to a value representing a number of pixels defining a horizontal line within the frame data; and

if the number of clock cycles is equal to the value, then the method includes,

identifying an end of a horizontal line within the frame of image data.

20. The method of claim 19, wherein subsequent to the method operation of identifying an end of a horizontal line within the frame of image data, the method includes,

counting the number of clock cycles;

comparing the number of clock cycles to a value representing a non-display period between horizontal lines within the frame data; and

if the number of clock cycles is equal to the value, then the method includes,

identifying a beginning of a next horizontal line within the frame of image data.