MEMORY ARCHITECTURE WITH ENHANCED OVER-ERASE TOLERANT CONTROL GATE SCHEME

• US 20070008775A1
• Filed: 07/11/2005
• Published: 01/11/2007
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Nguyen, Victor, Telecco, Nicola
• Granted Patent: US 7,180,779 B2
• Time in Patent Office: Days
• US Class Current: 365/185.300
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing

Abstract

The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and a negative bias voltage that is lower than a threshold voltage of an over-erased memory cell is also applied to at least one other selected memory cell that is in the same row as the target memory cell. Applying a negative bias voltage to adjacent or proximate memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.

Claims

1. A nonvolatile memory device comprising:

a plurality of memory cells arranged in an array of rows and columns, each of the plurality of memory cells further comprising at least one control gate;

a plurality of control gate circuits coupled to each of said memory cell control gates; and

a read voltage driver coupled to said plurality of control gate circuits and a negative bias voltage driver coupled to said plurality of control gate circuits, said plurality of control gate circuits configured to selectively couple said read voltage voltage driver to at least one target memory cell control gate in at least one selected row, said plurality of control gate circuits configured to selectively couple said negative bias voltage driver to at least one memory cell control gate in each of said at least one selected row as said at least one target memory cell.

2. The memory device of claim 1 wherein each of said plurality of control gate circuits further comprise a control gate logic circuit and a control gate block.

3. The memory device of claim 1 wherein each of said plurality of control gate circuits is further configured to selectively couple said negative bias voltage driver to at least one memory cell control gate that is adjacent to said target memory cell.

4. The memory device of claim 1 wherein each of said plurality of control gate circuits is further configured to selectively couple said negative bias voltage driver to at least one memory cell control gate that is proximate to, but not adjacent to, said target memory cell.

5. The memory device of claim 1 further comprising at least one service read voltage driver.

6. The memory device of claim 5 wherein each of said plurality of control gate circuits is further configured to selectively couple said service read voltage driver to at least one memory cell control gate that is adjacent to at least one target memory cell.

7. The memory device of claim 5 wherein each of said plurality of control gate circuits is further configured to selectively couple said service read voltage driver to at least one memory cell control gate that is adjacent to and in each of said at least one selected row as said at least one target memory cell;

and

each of said plurality of control gate circuits is configured to selectively couple said negative bias voltage driver to at least one memory cell control gate in each of said at least one selected row, and proximate to said at least one target memory cell.

8. The memory device of claim 1 further comprising a word line coupled to said plurality of memory cells, said word line configured to activate or select a row of memory cells.

9. The memory device of claim 1 wherein said negative bias voltage driver provides a voltage below or less than a threshold voltage of an over-erased memory cell.

10. A nonvolatile memory device comprising:

a plurality of twin MONOS memory units arranged in an array of rows and columns, each of the plurality of twin MONOS memory units including a plurality of memory cells, said plurality of memory cells each having a corresponding memory cell control gate;

a plurality of control gate circuits correspondingly coupled to said memory cell control gates;

a read voltage driver;

a service read voltage driver;

a negative bias voltage driver; and

said plurality of control gate circuits configured to selectively couple said read voltage driver to at least one target memory unit, said plurality of control gate circuits further configured to selectively couple said service read voltage driver to at least one other memory unit that is adjacent to and in a same row as said at least one target memory unit, said plurality of control gate circuits further configured to selectively couple said negative bias voltage driver to at least one other memory unit that is proximate to and in the same row as said at least one target memory unit.

11. The memory device of claim 10 further comprising a word line coupled to said plurality of twin MONOS memory units, said word line configured to activate or select a row of twin MONOS memory units.

12. The memory device of claim 10 wherein said negative bias voltage driver provides a voltage below or less than a threshold voltage of an over-erased memory cell.

13. A method of reducing an effect of over-erased nonvolatile memory cells, the method comprising:

arranging a plurality of nonvolatile memory cells having control gates in an array of rows and columns;

applying a read voltage to at least one target memory cell control gate; and

applying a negative bias voltage to at least one memory cell control gate that is proximate to and in a same row as said at least one target memory cell.

14. The method of claim 13 wherein applying said negative bias voltage is applied to said at least one memory cell control gate that is adjacent to said at least one target memory cell.

15. The method of claim 13 wherein a negative bias voltage is applied to said at least one memory cell control gate that is proximate to, but not adjacent to, said at least one target memory cell.

16. The method of claim 13 further comprising the step of applying a service read voltage to at least one other memory cell control gate that is adjacent to and in the same row as said at least one target memory cell.

17. The method of claim 13 further comprising the step of activating a word line to select a row of memory cells.

18. The method of claim 13 wherein applying a negative bias voltage applies a voltage that is below or less than a threshold voltage of an over-erased memory cell.

19. The method of claim 13 wherein applying a negative bias voltage to at least one memory cell control gate shuts off at least one over-erased memory cell.