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MEMORY ARCHITECTURE WITH ENHANCED OVER-ERASE TOLERANT CONTROL GATE SCHEME

  • US 20070008775A1
  • Filed: 07/11/2005
  • Published: 01/11/2007
  • Est. Priority Date: 07/11/2005
  • Status: Active Grant
First Claim
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1. A nonvolatile memory device comprising:

  • a plurality of memory cells arranged in an array of rows and columns, each of the plurality of memory cells further comprising at least one control gate;

    a plurality of control gate circuits coupled to each of said memory cell control gates; and

    a read voltage driver coupled to said plurality of control gate circuits and a negative bias voltage driver coupled to said plurality of control gate circuits, said plurality of control gate circuits configured to selectively couple said read voltage voltage driver to at least one target memory cell control gate in at least one selected row, said plurality of control gate circuits configured to selectively couple said negative bias voltage driver to at least one memory cell control gate in each of said at least one selected row as said at least one target memory cell.

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