MEMORY ARCHITECTURE WITH ENHANCED OVER-ERASE TOLERANT CONTROL GATE SCHEME
First Claim
1. A nonvolatile memory device comprising:
- a plurality of memory cells arranged in an array of rows and columns, each of the plurality of memory cells further comprising at least one control gate;
a plurality of control gate circuits coupled to each of said memory cell control gates; and
a read voltage driver coupled to said plurality of control gate circuits and a negative bias voltage driver coupled to said plurality of control gate circuits, said plurality of control gate circuits configured to selectively couple said read voltage voltage driver to at least one target memory cell control gate in at least one selected row, said plurality of control gate circuits configured to selectively couple said negative bias voltage driver to at least one memory cell control gate in each of said at least one selected row as said at least one target memory cell.
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Accused Products
Abstract
The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and a negative bias voltage that is lower than a threshold voltage of an over-erased memory cell is also applied to at least one other selected memory cell that is in the same row as the target memory cell. Applying a negative bias voltage to adjacent or proximate memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.
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Citations
19 Claims
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1. A nonvolatile memory device comprising:
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a plurality of memory cells arranged in an array of rows and columns, each of the plurality of memory cells further comprising at least one control gate;
a plurality of control gate circuits coupled to each of said memory cell control gates; and
a read voltage driver coupled to said plurality of control gate circuits and a negative bias voltage driver coupled to said plurality of control gate circuits, said plurality of control gate circuits configured to selectively couple said read voltage voltage driver to at least one target memory cell control gate in at least one selected row, said plurality of control gate circuits configured to selectively couple said negative bias voltage driver to at least one memory cell control gate in each of said at least one selected row as said at least one target memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A nonvolatile memory device comprising:
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a plurality of twin MONOS memory units arranged in an array of rows and columns, each of the plurality of twin MONOS memory units including a plurality of memory cells, said plurality of memory cells each having a corresponding memory cell control gate;
a plurality of control gate circuits correspondingly coupled to said memory cell control gates;
a read voltage driver;
a service read voltage driver;
a negative bias voltage driver; and
said plurality of control gate circuits configured to selectively couple said read voltage driver to at least one target memory unit, said plurality of control gate circuits further configured to selectively couple said service read voltage driver to at least one other memory unit that is adjacent to and in a same row as said at least one target memory unit, said plurality of control gate circuits further configured to selectively couple said negative bias voltage driver to at least one other memory unit that is proximate to and in the same row as said at least one target memory unit. - View Dependent Claims (11, 12)
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13. A method of reducing an effect of over-erased nonvolatile memory cells, the method comprising:
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arranging a plurality of nonvolatile memory cells having control gates in an array of rows and columns;
applying a read voltage to at least one target memory cell control gate; and
applying a negative bias voltage to at least one memory cell control gate that is proximate to and in a same row as said at least one target memory cell. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification