METHODS FOR OPERATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE

• US 20070008778A1
• Filed: 09/25/2006
• Published: 01/11/2007
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited), Marvell Semiconductor (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Wang, Chih-Hsin
• Granted Patent: US 7,613,041 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

Methods and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a third conductive region. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism in device operations. The injection filter permits transporting of charge carriers of one polarity type from the first conductive region, through the filter, and through the second conductive region to the third conductive region while blocking the transport of charge carriers of an opposite polarity from the second conductive region to the first conductive region. The present invention further provides an energy band engineering method permitting the devices be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

Claims

1. A method operating a semiconductor device having a first conductive region, a second conductive region disposed adjacent to and insulated from the first conductive region, a third conductive region disposed adjacent to and insulated from the second conductive region, and a strain source providing a mechanical stress to at least one of the first and the second conductive regions, the method comprising the steps of:

applying a first voltage to the first conductive region;

applying a second voltage to the second conductive region; and

applying a third voltage to the third conductive region to inject charge carriers from the first conductive region through the second conductive region into the third conductive region.

2. The method of claim 1, wherein the charge carriers are electrons.

3. The method of claim 1, wherein the charge carriers are light-holes.

4. A method operating a nonvolatile memory cell having a plurality of states, the memory cell comprising a first conductive region, a second conductive region disposed adjacent to and insulated from the first conductive region, a third region disposed adjacent to and insulated from the second conductive region, a strain source providing a mechanical stress to at least one of the first and the second conductive regions, and spaced-apart source and drain regions of a first conductivity type in a body of a semiconductor of a second conductivity type, the method comprising the steps of:

applying a first voltage to the first conductive region;

applying a second voltage to the second conductive region;

applying a body voltage to the body;

applying a source voltage to the source region; and

applying a drain voltage to the drain region to establish one of the plurality of states of the memory cell by injecting charge carriers from the first conductive region through the second conductive region into the third region.

5. The method of claim 4, wherein the memory cell further comprises an injection filter permitting charge carriers of one polarity type transporting from the first conductive region through the second conductive region to the third region and substantially blocking charge carriers of an opposite polarity type transporting from the second conductive region to the first conductive region.

6. The method of claim 4, wherein the memory cell stores one of the plurality of states by storing a discrete amount of charges on the third region.

7. The method of claim 4, wherein the body voltage, the source voltage, and the drain voltage are set at a first voltage setting to establish the memory cell in a first state of the plurality of states, and the method further comprises:

applying a second voltage setting to the body voltage, the source voltage, and the drain voltage to establish the memory cell in a second state of the plurality of states;

applying a third voltage setting to the body voltage, the source voltage, and the drain voltage to establish the memory cell in a third state of the plurality of states; and

applying a fourth voltage setting to the body voltage, the source voltage, and the drain voltage to establish the memory cell in a fourth state of the plurality of states.

8. The method of claim 7, wherein an amount of charges on the third region in the first state is less than an amount of charges on the third region in the second state, an amount of charges on the third region in the second state is less than an amount of charges on the third region in the third state, and an amount of charges on the third region in the third state is less than an amount of charges on the third region in the fourth state.

9. The method of claim 4, wherein the first voltage and the second voltage are set at a first voltage setting to establish the memory cell in a first state of the plurality of states, and the method further comprises:

applying a second voltage setting to the first voltage and the second voltage to establish the memory cell in a second state of the plurality of states;

applying a third voltage setting to the first voltage and the second voltage to establish the memory cell in a third state of the plurality of states; and

applying a fourth voltage setting to the first voltage and the second voltage to establish the memory cell in a fourth state of the plurality of states.

10. The method of claim 9, wherein an amount of charges on the third region in the first state is less than an amount of charges on the third region in the second state, an amount of charges on the third region in the second state is less than an amount of charges on the third region in the third state, and an amount of charges on the third region in the third state is less than an amount of charges on the third region in the fourth state.

11. The method of claim 4, wherein the third region comprises material selected from the group consisting of conductive material, nano-particles, and dielectrics.

12. The method of claim 4, wherein the charge carriers are electrons.

13. The method of claim 4, wherein the charge carriers are light-holes.

14. A method operating a nonvolatile memory cell, the memory cell comprising a first conductive region having charge carriers, a second conductive region, an injection filter including a blocking dielectric having a band offset with respect to the first conductive region, a third region disposed adjacent to and insulated from the second conductive region, and spaced-apart source and drain regions of a first conductivity type in a body of a semiconductor of a second conductivity type, the method comprising the steps of:

applying a first voltage to the first conductive region; and

applying a second voltage to the second conductive region to substantially block the charge carriers transporting from the first conductive region to the second conductive region.

15. The method of claim 14, wherein the charge carriers are electrons and the band offset is a conduction band offset, and wherein a magnitude of a voltage difference between the first and the second voltages is smaller than a sum of the conduction band offset and an energy band gap of the second conductive region minus a flat-band voltage of the injection filter.

16. The method of claim 15, wherein the magnitude of the voltage difference is in a range of about 1 V to about 2 V.

17. The method of claim 14, wherein the charge carriers are holes and the band offset is a valence band offset, and wherein a voltage difference between the first and the second voltages is smaller than a sum of the valence band offset and a flat-band voltage of the injection filter.

18. The method of claim 17, wherein the voltage difference is in a range of about 2 V to about 2.5 V.

19. A method of operating a nonvolatile memory cell, the memory cell comprising a first conductive region, a second conductive region, an injection filter establishing one or more barriers in between the first and the second conductive regions where each barrier has an entrance barrier height at an entrance and an exit barrier height at an exit for charge carriers traveling in a direction from the entrance to the exit, a third region disposed adjacent to and insulated from the second conductive region, and spaced-apart source and drain regions of a first conductivity type in a body of a semiconductor of a second conductivity type, the method comprising the steps of:

applying a first voltage to the first conductive region;

applying a second voltage to the second conductive region;

said first voltage and said second voltage applied, for each barrier, to cause the entrance barrier height and the exit barrier height to be greater than a carrier energy level for the charge carriers and the exit barrier height to be less than or equal to the entrance barrier height whereby each barrier is trapezoidal-shaped.

20. The method of claim 19, wherein the memory cell further comprising a strain source providing a mechanical stress to at least one of the first and the second conductive regions.