Method and apparatus to support efficient check-point and role-back operations for flow-controlled queues in network devices

• US 20070008985A1
• Filed: 06/30/2005
• Published: 01/11/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wolrich, Gilbert, Wilkinson, Hugh, Jain, Sanjeev, Lakshmanamurthy, Sridhar
• Granted Patent: US 7,505,410 B2
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: H04L 49/1523 Parallel switch fabric planes
• CPC Class Codes: H04L 49/552 by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04L 49/557 Error correction, e.g. fault recovery or fault tolerance
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal

Abstract

Method and apparatus to support efficient check-point and role-back operations for flow-controlled queues in network devices. The method and apparatus employ queue descriptors to manage transfer of data from corresponding queues in memory into a switch fabric. In one embodiment, each queue descriptor includes an enqueue pointer identifying a tail cell of a segment of data scheduled to be transferred from the queue, a schedule pointer identifying a head cell of the segment of data, and a commit pointer identifying a most recent cell in the segment of data to be successfully transmitted into the switch fabric. In another embodiment, the queue descriptor further includes a scheduler sequence number; and a committed sequence number that are employed in connection with transfers of data from queues containing multiple segments. The various pointers and sequence numbers are employed to facilitate efficient check-point and roll-back operations relating to unsuccessful transmissions into the switch fabric.

Claims

1. A method comprising:

employing queue descriptors to manage transfer of data from corresponding queues in a memory store into a switch fabric, each queue descriptor including,

an enqueue pointer identifying a tail cell of a segment of data scheduled to be transferred from the queue;

a schedule pointer identifying a head cell of the segment of data scheduled to be transferred from the queue; and

a commit pointer identifying a most recent cell in the segment of data to be successfully transmitted into the switch fabric.

2. The method of claim 1, further comprising:

receiving a schedule request to transfer a segment of data, the segment of data including a series of cells beginning at a head cell and ending at a tail cell;

identifying a corresponding queue descriptor to manage the transfer of the segment of data, the queue descriptor including an enqueue pointer pointing to the tail cell; and

updating the schedule pointer of the corresponding queue descriptor to point to the head cell for the segment of data.

3. The method of claim 2, further comprising:

transferring a first portion of the segment of data from a memory store into a transmit buffer;

determining if a switch fabric into which the segment of data is to be transmitted is available;

transmitting the first portion of the segment of data from the buffer into the switch fabric if it is available; and

updating the commit pointer of the queue descriptor to indicate that the first portion of the segment of data has been successfully transferred.

4. The method of claim 3, further comprising:

initiating transfer of a second portion of the segment of data from the memory store into the transmit buffer;

determining that the switch fabric is not available to receive a transmission of the second portion of the segment of data; and

performing a roll-back operation in response thereto, the roll-back operation including,

dropping the second portion of the segment of data; and

resetting the schedule pointer to point to the same cell as the commit pointer.

5. The method of claim 4, further comprising:

rescheduling transfer of the second portion of the segment of data using the queue descriptor.

6. The method of claim 4, further comprising:

dropping any cells in the second portion of the segment of data that are in transit from the memory store to the transmit buffer when the roll-back operation is initiated.

7. The method of claim 1, wherein a queue descriptor further includes:

a scheduler sequence number; and

a committed sequence number,

wherein the queue descriptor is used to manage transfer of a set of segments of data stored in a corresponding queue in a memory store, with the scheduler sequence number identifying a first segment of data scheduled to be transferred from the queue and the committed sequence number identifying a most recent segment of data to be successfully transmitted into the switch fabric.

8. The method of claim 7, further comprising:

transferring a plurality of segments of data from a memory store into a transmit buffer;

initiating transfer of the plurality of segments of data from the transmit buffer into a switch fabric;

determining, during the transfer, that the switch fabric is not available to receive a transmission of further segments of data; and

performing a roll-back operation in response thereto, the roll-back operation including,

dropping the portion of the segments of data that were transferred from the memory store into the transmit buffer but where not transmitted into the switch fabric; and

updating the queue descriptor to reflect the portion of the segments of data that were dropped.

9. The method of claim 8, further comprising:

determining a first sequence number in a queue marked for segment drop; and

storing the first sequence number as a restart sequence number.

10. The method of claim 8, further comprising:

resetting the scheduler pointer to point to the same cell as the commit pointer; and

resetting the scheduler sequence number to equal the committed sequence number.

11. The method of claim 1, wherein a queue descriptor further includes:

a scheduler cell count identifying a number of cells within a corresponding segment of data scheduled to be transferred; and

a committed cell count identifying a number of cells within the segment that have been successfully transmitted into the switch fabric,

wherein the committed cell count is updated in response to a successful transmission of one or more cells.

12. An apparatus, comprising:

a queue management engine, to manage transfer of data stored in memory queues into a switch fabric using corresponding queue descriptors, each queue descriptor including,

an enqueue pointer identifying a tail cell of a segment of data scheduled to be transferred from the queue;

a schedule pointer identifying a head cell of the segment of data scheduled to be transferred from the queue; and

a commit pointer identifying a most recent cell in the segment of data to be successfully transmitted into the switch fabric;

a buffer manager, to manage transmit buffers in which data to be transferred is temporarily stored prior to being transmitted into the switch fabric; and

a transmit engine, to effect transmission of data from the transmit buffers into the switch fabric.

13. The apparatus of claim 12, further comprising:

a primary scheduler, to provide schedule request to the queue management engine, each schedule request to request transfer of a corresponding segment of data into the switch fabric.

14. The apparatus of claim 12, wherein the apparatus comprises a network processor unit further including a plurality of compute engines.

15. The apparatus of claim 14, wherein at least a portion of the operations performed by at least one of the queue management engine, buffer manager, and transmit engine is effected via execution of corresponding instruction threads on selected compute engines.

16. The apparatus of claim 12, wherein a queue descriptor further includes:

a scheduler sequence number; and

a committed sequence number,

wherein the queue descriptor is used to manage transfer of a set of segments of data stored in a corresponding queue in a memory store, with the scheduler sequence number identifying a first segment of data scheduled to be transferred from the queue and the committed sequence number identifying a most recent segment of data to be successfully transmitted into the switch fabric.

17. The apparatus of claim 12, wherein the apparatus comprises a fabric interface chip.

18. A network line card, comprising:

a circuit board including a backplane interface having a plurality of signal lines, at least a portion of which may be used to transfer data and control signals to a switch fabric;

a static random access memory (SRAM) memory store, operatively-coupled to the circuit board;

a dynamic random access memory (DRAM) memory store, operatively-coupled to the circuit board;

a network processor unit, operatively-coupled to the circuit board and including,

a plurality of compute engines, each to support execution of a plurality of instruction threads;

a DRAM interface, communicatively-coupled to the plurality of compute engines and the DRAM store;

as SRAM interface, communicatively-coupled to the plurality of compute engines and the SRAM store;

a media switch fabric interface, communicatively-coupled to the plurality of compute engines and the backplane interface;

a plurality of transmit buffers, communicatively coupled to the media switch fabric interface or integrated therewith; and

at least one non-volatile storage device, integrated on the NPU or operatively-coupled to the circuit board and communicatively-coupled to the NPU, to store instructions that if executed on selected compute engines facilitates operation of a plurality of operational blocks, including,

a queue management engine, to manage transfer of data stored in memory queues in the DRAM store into a switch fabric using corresponding queue descriptors, each queue descriptor including,

an enqueue pointer identifying a tail cell of a segment of data scheduled to be transferred from the queue;

a schedule pointer identifying a head cell of the segment of data scheduled to be transferred from the queue; and

a commit pointer identifying a most recent cell in the segment of data to be successfully transmitted into the switch fabric;

a buffer manager, to manage the plurality of transmit buffers into which data to be transferred is temporarily stored prior to being transmitted into the switch fabric; and

a transmit engine, to effect transmission of data from the transmit buffers into the switch fabric.

19. The network line card of claim 18, wherein the network line card comprises an Advanced Switching (AS) endpoint.

20. The network line card of claim 18, wherein a queue descriptor further includes:

a scheduler sequence number; and

a committed sequence number,

wherein the queue descriptor is used to manage transfer of a set of segments of data stored in a corresponding queue in the DRAM store, with the scheduler sequence number identifying a first segment of data scheduled to be transferred from the queue and the committed sequence number identifying a most recent segment of data to be successfully transmitted into the switch fabric.