Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current

• US 20070010090A1
• Filed: 09/07/2006
• Published: 01/11/2007
• Est. Priority Date: 09/07/2001
• Status: Active Grant

• Current Assignee: Dong-Kyun Nam, Heon-Jong Shin, Hyung Tae Ji
• Original Assignee: Dong-Kyun Nam, Heon-Jong Shin, Hyung Tae Ji
• Inventors: Shin, Heon-jong, Nam, Dong-kyun, Ji, Hyung tae
• Granted Patent: US 7,704,892 B2
• Time in Patent Office: Days
• US Class Current: 438/629
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/66409 Unipolar field-effect transistors
• CPC Class Codes: H01L 29/80 with field effect produced by a PN or other rectifying junction gate , i.e. potential-jump barrier

Abstract

A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.

Claims

1. A method for manufacturing a semiconductor device having a local interconnection layer, the method comprising:

implanting impurity ions into a semiconductor substrate, on which an isolation layer and a gate pattern are formed, and forming a junction layer on the semiconductor substrate;

etching an etch stopper having at least one layer on the isolation layer and the junction layer and forming an etch stopper pattern for preventing the etching of the isolation layer;

etching an interlayer dielectric (ILD) layer on the junction layer, the gate pattern, and the etch stopper, and forming a contact hole on which a local interconnection layer is to be formed; and

forming the local interconnection layer by filling the contact hole with a conductive material.

2. The method of claim 1, wherein the etch stopper pattern covers the isolation layer and part of the junction layer.

3. The method of claim 1, wherein the etch stopper pattern covers part of the isolation layer.

4. The method of claim 1, wherein the etch stopper pattern includes a silicon nitride (Si₃N₄) layer.

5. The method of claim 4, wherein the thickness of the silicon nitride (Si₃N₄) layer is 300-700 Å

.

6. The method of claim 1, wherein the etch stopper pattern remains on the isolation layer on which the local interconnection layer is not formed.

7. The method of claim 1, wherein the etch stopper pattern is comprised of a first silicon nitride (Si₃N₄) layer, a silicon oxide (SiO₂) layer, and a second silicon nitride (Si₃N₄) layer.

8. The method of claim 7, wherein the first silicon nitride (Si₃N₄) layer and the silicon oxide (SiO₂) layer remain on the junction layer on which the local interconnection layer is not formed.

9. The method of claim 7, wherein the first silicon nitride (Si₃N₄) layer, the silicon oxide (SiO₂) layer, and the second silicon nitride (Si₃N₄) layer remain on the isolation layer on which the local interconnection layer is not formed.