METHOD OF ROOM TEMPERATURE GROWTH OF SIOx ON SILICIDE AS AN ETCH STOP LAYER FOR METAL CONTACT OPEN OF SEMICONDUCTOR DEVICES

• US 20070010093A1
• Filed: 07/06/2005
• Published: 01/11/2007
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lavoie, Christian, Wang, Yun-Yu, Mello, Kevin, Murray, Conal, Oonk, Matthew
• Granted Patent: US 7,538,029 B2
• Time in Patent Office: Days
• US Class Current: 438/655
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

Silicide is protected during MC RIE etch by first forming an oxide film over the silicide and, after performing MC RIE etch, etching the oxide film. The oxide film is formed from a film of alloyed metal-silicon (M-Si) on the layer of silicide, then wet etching the metal-silicon. An ozone plasma treatment process can be an option to densify the oxide film. The oxide film may be etched by oxide RIE or wet etch, using 500:1 DHF.

Claims

1. A method of forming a semiconductor device having a layer of silicide and a contact opening extending through an overlying dielectric layer to the layer of silicide, the method comprising the steps of:

before forming the contact opening, forming an oxide film over the layer of silicide; and

after forming the contact opening, removing the oxide film to expose the underlying layer of silicide.

2. The method of claim 1, wherein the step of removing the oxide film comprises:

performing oxide reactive ion etching (RIE).

3. The method of claim 1, wherein the step of removing the oxide film comprises:

using 500;

1 DHF.

4. The method of claim 1, further comprising the step of:

before applying the dielectric layer, depositing a nitride capping layer.

5. The method of claim 1, wherein the step of forming the oxide film comprises:

first forming a film of alloyed metal-silicon (M-Si) on the layer of silicide;

then, forming the oxide film by wet etching the metal-silicon.

6. The method of claim 5, wherein:

the metal in the alloyed metal-silicon (M-Si) is selected from the group consisting of where M can be Ti, Ni, Co, or other transition metal.

7. The method of claim 5, wherein:

the wet etching comprises an etch solution of H₂SO₄ with H₂O₂.

8. The method of claim 5, further comprising the step of:

performing an ozone plasma treatment to densify the oxide.

9. The method of claim 1, wherein the device is a field effect transistor (FET), and the silicide comprises source and drain regions of the FET.

10. A method of protecting silicide during MC RIE etch comprising:

before performing MC RIE etch, forming an oxide film over the silicide.

11. The method of claim 10, further comprising:

forming a nitride layer over the oxide film.

12. The method of claim 11, further comprising:

performing an ozone plasma treatment to densify the oxide.

13. The method of claim 11, further comprising:

after performing MC RIE etch, etching the oxide film.

14. The method of claim 13, wherein the step of etching the oxide film comprises:

performing oxide reactive ion etching (RIE).

15. The method of claim 13, wherein the step of etching the oxide film comprises:

a wet etch using 500;

1 DHF.

16. A semiconductor device comprising:

a layer of silicide;

a layer of oxide over the silicide; and

a layer of nitride over the layer of oxide.

17. The semiconductor device of claim 16, further comprising:

a layer of dielectric over the layer of nitride.

18. The semiconductor device of claim 17, further comprising:

a contact opening extending through the dielectric layer to the silicide.

19. The semiconductor device of claim 16, wherein the layer of oxide is formed from alloyed metal silicon (M-Si) and the Si in the composition of the M-Si, the Si is about 10%-30% by atomic percentage, preferably about 15%-25% by atomic percentage and most preferably about 20% by atomic percentage.

20. The semiconductor device of claim 16, wherein the semiconductor device is a FET having source and drain regions and a gate electrode, and the layer of silicide is over the source and drain regions and the gate electrode.