Digital baseband receiver with DC discharge and gain control circuits

• US 20070010223A9
• Filed: 04/27/2004
• Published: 01/11/2007
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Kazakevich, Leonid, Demir, Alpaslan, Ozluturk, Fatih, Narayan, Geetha
• Granted Patent: US 7,280,812 B2
• Time in Patent Office: Days
• US Class Current: 455/205
• CPC Class Codes: H03D 3/008 Compensating DC offsets
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A digital baseband (DBB) receiver for receiving and processing a wireless communication signal. The DBB receiver includes at least one low noise amplifier (LNA), at least one demodulator, a direct current (DC) discharge circuit and an LNA control circuit. The LNA selectively amplifies the communication signal. The demodulator outputs analog real and imaginary signal components on real and imaginary signal paths, respectively, in response to receiving the communication signal from the LNA. The DC discharge circuit selectively discharges DC accumulating on at least one of the real and imaginary signal paths. The LNA control circuit turns the LNA on or off.

Claims

1. A digital baseband (DBB) receiver comprising:

(a) means for amplifying an incoming signal;

(b) means for generating real and imaginary analog signal components based on the incoming signal;

(c) means for digitizing the signal components;

(d) means for providing an estimate of the direct current (DC) residing on each of the digitized components;

(e) means for subtracting the DC estimates from each respective one of the digitized signal components to provide an adjusted real signal component and an adjusted imaginary signal component;

(f) means for providing estimates of the absolute power and magnitude of the adjusted signal components; and

(g) means for enabling or disabling the amplifying means based on the absolute power and magnitude estimate.

39. The DBB receiver of claim 1 wherein means (a) - (g) are incorporated in an integrated circuit (IC) which is comprised by the DBB receiver.

40. The DBB receiver of claim 1 wherein means (a) - (g) are incorporated in a wireless transmit/receive unit (WTRU) which comprises the DBB receiver.

2. In a digital baseband (DBB) receiver for receiving and processing an incoming signal, a method comprising:

(a) generating real and imaginary analog signal components based on the incoming signal;

(b) digitizing the signal components;

(c) providing an estimate of the direct current (DC) residing on each of the digitized components;

(d) subtracting the DC estimates from each respective one of the digitized signal components to provide an adjusted real signal component and an adjusted imaginary signal component;

(e) providing estimates of the absolute power and magnitude of the adjusted signal components; and

(f) selectively amplifying the incoming signal based on the absolute power and magnitude estimate.

3. A digital baseband (DBB) receiver for receiving and processing an incoming signal, the receiver comprising:

(a) means for generating real and imaginary analog signal components based on the incoming signal;

(b) means for digitizing the signal components;

(c) means for providing an estimate of the direct current (DC) power residing on each of the digitized components;

(d) means for comparing the DC power estimate to a predetermined value; and

(e) means for selectively discharging DC from the digitized components based on the difference between the DC power estimate and the predetermined value.

41. The DBB receiver of claim 3 wherein means (a) - (e) are incorporated in an integrated circuit (IC) which is comprised by the DBB receiver.

42. The DBB receiver of claim 3 wherein means (a) - (e) are incorporated in a wireless transmit/receive unit (WTRU) which comprises the DBB receiver.

4. In a digital baseband (DBB) receiver for receiving and processing an incoming signal, a method comprising:

(a) generating real and imaginary analog signal components based on the incoming signal;

(b) digitizing the signal components;

(c) providing an estimate of the direct current (DC) power residing on each of the digitized components;

(d) comparing the DC power estimate to a predetermined value; and

(e) selectively discharging DC from the digitized components based on the difference between the DC power estimate and the predetermined value.

5-8. -8. (canceled)

9. A digital baseband (DBB) receiver for receiving and processing a wireless communication signal, the DBB receiver comprising:

(a) at least one low noise amplifier (LNA) which selectively amplifies the communication signal;

(b) at least one demodulator which outputs analog real and imaginary signal components on real and imaginary signal paths, respectively, in response to receiving the communication signal from the LNA;

(c) a direct current (DC) discharge circuit for selectively discharging direct current accumulating on at least one of the real and imaginary signal paths; and

(d) an LNA control circuit for turning the LNA on or off.

10. The DBB receiver of claim 9 further comprising:

(e) a first high pass filter (HPF) circuit in communication with the real signal path; and

(f) a second HPF circuit in communication with the imaginary signal path, wherein each of the first and second HPF circuits includes at least one capacitor and at least one switch in parallel with the capacitor, the switches being controlled by the DC discharge circuit to selectively flush accumulated DC from the capacitors.

11. The DBB receiver of claim 10 further comprising:

(g) a first digital gain control circuit having an input in communication with the first HPF circuit;

(h) a second digital gain control circuit having an input in communication with the second HPF circuit; and

(i) a DC offset and normalization compensation module in communication with respective outputs of the first and second digital gain circuits, an input to the DC discharge circuit and an input to the LNA control circuit, wherein the DC offset and normalization compensation module maintains the output of the DBB receiver at a constant output power level.

12. The DBB receiver of claim 9 further comprising:

(e) a first high pass filter (HPF) circuit in communication with the real signal path; and

(f) a second HPF circuit in communication with the imaginary signal path, wherein each of the first and second HPF circuits includes at least one capacitor and at least one transistor in communication with the capacitor, the transistors being controlled by the DC discharge circuit to selectively flush accumulated DC from the capacitors.

13. The DBB receiver of claim 12 further comprising:

(g) a first digital gain control circuit having an input in communication with the first HPF circuit;

(h) a second digital gain control circuit having an input in communication with the second HPF circuit; and

(i) a DC offset and normalization compensation module in communication with respective outputs of the first and second digital gain circuits, an input to the DC discharge circuit and an input to the LNA control circuit, wherein the DC offset and normalization compensation module maintains the output of the DBB receiver at a constant level.

43. The DBB receiver of claim 9 wherein the LNA, the demodulator, the DC discharge circuit and the LNA control circuit are incorporated in an integrated circuit (IC) which is comprised by the DBB receiver.

44. The DBB receiver of claim 9 wherein the LNA, the demodulator, the DC discharge circuit and the LNA control circuit are incorporated in a wireless transmit/receive unit (WTRU) which comprises the DBB receiver.

14. A digital baseband (DBB) receiver for receiving and processing a wireless communication signal, the DBB receiver comprising:

(a) at least one demodulator which outputs analog real and imaginary signal components on real and imaginary signal paths, respectively, in response to receiving the communication signal; and

(b) a direct current (DC) discharge circuit for selectively discharging direct current accumulating on at least one of the real and imaginary signal paths.

15. The DBB receiver of claim 14 further comprising:

(c) a first high pass filter (HPF) circuit in communication with the real signal path; and

(d) a second HPF circuit in communication with the imaginary signal path, wherein each of the first and second HPF circuits includes at least one capacitor and at least one switch in parallel with the capacitor, the switches being controlled by the DC discharge circuit to selectively flush accumulated DC from the capacitors.

16. The DBB receiver of claim 15 further comprising:

(e) a first digital gain control circuit having an input in communication with the first HPF circuit;

(f) a second digital gain control circuit having an input in communication with the second HPF circuit; and

(g) a DC offset and normalization compensation module in communication with respective outputs of the first and second digital gain circuits and an input to the DC discharge circuit, wherein the DC offset and normalization compensation module maintains the output of the DBB receiver at a constant output power level.

17. The DBB receiver of claim 14 further comprising:

(c) a first high pass filter (HPF) circuit in communication with the real signal path; and

(d) a second HPF circuit in communication with the imaginary signal path, wherein each of the first and second HPF circuits includes at least one capacitor and at least one transistor in communication with the capacitor, the transistors being controlled by the DC discharge circuit to selectively flush accumulated DC from the capacitors.

18. The DBB receiver of claim 17 further comprising:

(e) a first digital gain control circuit having an input in communication with the first HPF circuit;

(f) a second digital gain control circuit having an input in communication with the second HPF circuit; and

(g) a DC offset and normalization compensation module in communication with respective outputs of the first and second digital gain circuits and an input to the DC discharge circuit, wherein the DC offset and normalization compensation module maintains the output of the DBB receiver at a constant level.

45. The DBB receiver of claim 14 wherein the demodulator and the DC discharge circuit are incorporated in an integrated circuit (IC) which is comprised by the DBB receiver.

46. The DBB receiver of claim 14 wherein the demodulator and the DC discharge circuit are incorporated in a wireless transmit/receive unit (WTRU) which comprises the DBB receiver.

19-38. -38. (canceled)