Method and system for data-driven runtime alignment operation

• US 20070011441A1
• Filed: 07/08/2005
• Published: 01/11/2007
• Est. Priority Date: 07/08/2005
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Salapura, Valentina, Gschwind, Michael, Wu, Peng, Eichenberger, Alexandre
• Application Number:
  US11/176,988
• Publication Number:
  US 20070011441A1
• Time in Patent Office: Days
• US Class Current: 712/221
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/355 Indexed addressing
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 Operand accessing

Abstract

A method for processing instructions and data in a processor includes steps of: preparing an input stream of data for processing in a data path in response to a first set of instructions specifying a dynamic parameter; and processing the input stream of data in the same data path in response to a second set of instructions. A common portion of a dataflow is used for preparing the input stream of data for processing in response to a first set of instructions under the control of a dynamic parameter specified by an instruction of the first set of instructions, and for operand data routing based on the instruction specification of a second set of instructions during the processing of the input stream in response to the second set of instructions.

Claims

1. A method for processing instructions and data in a processor, the method comprising steps of:

preparing an input stream of data for processing in a data path in response to a first set of instructions specifying a dynamic parameter; and

processing the input stream of data in the same data path in response to a second set of instructions;

wherein a common portion of a dataflow is used for preparing the input stream of data for processing in response to the first set of instructions under the control of the dynamic parameter specified by an instruction of the first set of instructions, and for operand data routing based on the instruction specification of the second set of instructions during the processing of the input stream in response to the second set of instructions.

2. The method of claim 1, wherein the step of preparing the input stream of data comprises aligning the data by performing a conditional select operation using multiplexing logic embedded into a computational datapath, the conditional select logic being under the control of alignment information provided to the alignment instruction as a dynamic parameter.

3. The method of claim 2, wherein alignment is achieved in a first mode by selecting a first and a second element of a first value tuple, and in a second mode by selecting a second element of the first value tuple and a first element of a second value tuple, the tuples being stored in specified register input parameters, and storing the selected elements as a single value tuple in a specified register output parameter, the mode being selected by alignment information provided as a dynamic parameter.

4. The method of claim 3 wherein the alignment is performed in response to a data driven alignment operation wherein alignment information is specified as a dynamic parameter.

5. The method of claim 3 wherein the dynamic alignment parameter is stored in one of a vector register, floating point register, integer register, condition register, special purpose register, alignment register, or other register, the register encoded in either one of implicitly and explicitly in the instruction.

6. The method of claim 4 wherein the conditional select logic used to implement the dynamic data alignment under the control of the dynamic parameter is used to implement instruction-dependent data routing to implement at least one computational instruction.

7. The method of claim 5 wherein the at least one computational instruction is a double precision IEEE floating point complex arithmetic instruction.

8. The method of claim 5 wherein the instruction is specified as a Fixed-width RISC instruction targeting a microprocessor having a primary and secondary set of floating point registers, the output specifier being one of 32 paired floating point registers, a first and second input specifiers being one of 32 paired floating point registers, and the dynamic alignment being specified in a third input specifier as one of 32 paired floating point registers.

9. The method of claim 7 wherein the fixed-width RISC instruction has been generated using a compiler method equipped to extract SIMD parallelism from scalar code, the compiler method comprising steps of:

aligning devirtualization, by inserting the fixed-width RISC instruction, loop prolog code generation, including the steps of generating instructions to determine alignment at runtime and loading the information to at least one paired double precision floating register to serve as dynamic alignment specification for the generated PowerPC dynamic alignment instruction.

10. A processor comprising:

a primary register file;

a secondary register file; and

a processing pipeline for;

preparing an input stream of data for processing in a data path in response to a first set of instructions specifying a dynamic parameter; and

processing the input stream of data in the same data path in response to a second set of instructions,

wherein a common portion of the dataflow is used for preparing the input stream of data for processing in response to the first set of instructions under the control of the dynamic parameter specified by an instruction of the first set of instructions, and for operand data routing based on the instruction specification of the second set of instructions during the processing of the input stream in response to the second set of instructions.

11. The processor of claim 10 wherein the data preparation step comprises aligning the data using one of operand routing logic and an operand crossbar embedded into a computational datapath, the conditional select logic being under the control of alignment information provided to the alignment instruction as a dynamic parameter.

12. The processor of claim 10 wherein alignment is achieved in a first mode by selecting a first and a second element of a first value tuple, and in a second mode by selecting a second element of the first value tuple and a first element of a second value tuple, the tuples being stored in specified register input parameters, and storing the selected elements as a single value tuple in a specified register output parameter, the mode being selected by alignment information provided as a dynamic parameter.

13. The processor of claim 12 wherein the alignment is performed in response to a data driven alignment operation wherein alignment information is specified as a dynamic parameter, stored in one of a vector register, floating point register, integer register, condition register, special purpose register, alignment register, or other register, the register encoded either one of implicitly and explicitly in the instruction.

14. The processor of claim 13 further comprising an additional instruction word field for identifying each conditional cross select, wherein one or more bits in the dynamic alignment parameter comprise alignment information for multiple streams indicating alignment or misalignment for a received information stream.

15. The processor of claim 14 wherein the received information is then used to steer a plurality of selector circuits to extract information for the current stream.

16. The processor of claim 13 wherein the conditional select logic used to implement the dynamic data alignment under the control of the dynamic parameter is used to implement instruction-dependent data routing to implement at least one computational instruction.

17. The processor of claim 16 wherein the instruction is specified as a fixed-width RISC instruction targeting a microprocessor having a primary and secondary set of floating point registers, the output specifier being one of 32 paired floating point registers, a first and second input specifiers being one of 32 paired floating point registers, and the dynamic alignment being specified in a third input specifier as one of 32 paired floating point registers.

18. The processor of claim 17 wherein the fixed-width RISC instruction has been generated using a compiler method equipped to extract SIMD parallelism from scalar code, the compiler method comprising the steps of:

alignment devirtualization, by inserting the PowerPC dynamic alignment instruction;

loop prolog code generation, including the steps of generating instructions to determine alignment at runtime and loading the information to at least one paired double precision floating register to serve as dynamic alignment specification for the generated PowerPC dynamic alignment instruction.

19. A computer-readable medium comprising instructions for processing instructions and data in a processor, the medium comprising instructions for:

preparing an input stream of data for processing in a data path; and

processing the input stream of data in the same data path.

20. The medium of claim 19, wherein instructions target a data path including a common dataflow used for operand data routing based on the instruction specification of the said first set of instructions during the processing of the input stream in response to the said first set of instructions, and preparing the input stream of data for processing in response to the said second set of instructions under the control of the dynamic parameter specified by an instruction of said second set of instructions.

21. The medium of claim 19, wherein the step of preparing the input stream of data comprises aligning the data by performing a conditional select operation using multiplexing logic embedded into a computational datapath, the conditional select logic being under the control of alignment information provided to the alignment instruction as a dynamic parameter.

22. The medium of claim 19, wherein alignment is achieved in a first mode by selecting a first and a second element of a first value tuple, and in a second mode by selecting a second element of a first value tuple and a first element of a second value tuple, the tuples being stored in specified register input parameters, and storing the selected elements as a single value tuple in a specified register output parameter, the mode being selected by alignment information provided as a dynamic parameter.

23. The medium of claim 22 wherein alignment is achieved using a fixed-width RISC instruction targeting a microprocessor having a primary and secondary set of floating point registers, the output specifier being one of 32 paired floating point registers, a first and second input specifiers being one of 32 paired floating point registers, and the dynamic alignment being specified in a third input specifier as one of 32 paired floating point registers.

24. The medium of claim 20 wherein the instructions have been generated using a compiler method equipped to extract SIMD parallelism from scalar code, the compiler method comprising the steps of:

alignment devirtualization, by inserting the fixed-width RISC instruction, loop prolog code generation, including the steps of;

instruction generation to determine alignment at runtime; and

instruction generation to load to at least one paired double precision floating register the information that serves as dynamic alignment specification for the generated PowerPC dynamic alignment instruction.

25. A method comprising steps of:

extracting SIMD parallelism within a block of data received by packing isomorphic computation on adjacent memory accesses to vector operations;

aggregating static computation on stride-one accesses across the entire loop into operations to longer vectors

extracting SIMD parallelism across loop iterations;

transforming loads and storing from possibly unaligned vectors to aligned vectors using a stream-based alignment handling algorithm;

inserting the conditional cross-select alignment instructions to generate properly aligned data wherein alignment is achieved in a first mode by selecting a first and a second element of a first value tuple, and in a second mode by selecting a second element of a first value tuple and a first element of a second value tuple, the tuples being stored in specified register input parameters, and storing the selected elements as a single value tuple in a specified register output parameter, the mode being selected by alignment information provided as a dynamic parameter;

said conditional cross-select alignment instruction being capable of being executed using operand routing logic in a computational datapath.

flattening vectors to primitive types; and

mapping generic operations to physical vectors to one or more SIMD instructions.

26. The method of claim 25 wherein addresses are used to directly as dynamic alignment parameter.

27. The method of claim 25 wherein the dynamic alignment parameter is computed from at least two addresses and used directly as dynamic alignment parameter.

28. The method of claim 27, wherein the alignment parameter is computed using on of the subtraction and XOR operation on said two addresses.