Decompressor/PRPG for applying pseudo-random and deterministic test patterns
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Abstract
A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
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Citations
53 Claims
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1-33. -33. (canceled)
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34. A method for testing a circuit-under-test, comprising:
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simulating a pseudo-random phase of operation of the circuit-under-test, wherein the simulation comprises simulating faults in the circuit-under-test while pseudo-random test patterns are applied to the circuit-under-test;
identifying faults that are undetected by the pseudo-random phase of operation using results from the simulation; and
producing one or more compressed deterministic test patterns that target at least some of the faults that are undetected during the pseudo-random phase of operation, the compressed deterministic test patterns being applicable to the circuit-under-test during a deterministic phase of operation. - View Dependent Claims (35, 36, 37, 38, 39)
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40. A method for operating a decompressor/PRPG comprising:
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in a pseudo-random phase of operation;
inputting an initial value;
generating from the initial value a set of pseudo-random test patterns; and
outputting the pseudo-random test patterns;
in a deterministic phase of operation;
inputting a compressed deterministic test pattern;
decompressing the compressed deterministic test pattern into a decompressed deterministic test pattern as the compressed deterministic test pattern is being input, the decompressing including logically combining one or more bits of the compressed deterministic test pattern with bits stored within the decompressor/PRPG; and
outputting the decompressed deterministic test pattern. - View Dependent Claims (41, 42, 43, 44, 45)
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46. A circuit comprising:
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a decompressor/PRPG;
control circuitry coupled to the decompressor/PRPG and operable to cause the decompressor/PRPG to generate, in a pseudo-random phase of operation, a set of pseudo-random patterns and to generate, in a deterministic phase of operation, a set of decompressed deterministic test patterns from a set of provided compressed deterministic patterns, the control circuitry comprising one or more logic gates that receive the compressed deterministic patterns during the deterministic phase of operation and logically combine the compressed deterministic patterns with bits stored within the decompressor/PRPG;
circuit logic; and
scan chains coupled to the circuit logic and operable to receive test patterns generated by the decompressor/PRPG and to capture responses to the test patterns generated by the circuit logic, wherein the decompressor/PRPG is operable to decompress a compressed deterministic test pattern as the compressed deterministic test pattern is being provided to the decompressor/PRPG. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53)
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Specification