Providing high availability in a PCI-Express™ link in the presence of lane faults

• US 20070011549A1
• Filed: 06/24/2005
• Published: 01/11/2007
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sharma, Debendra
• Granted Patent: US 7,353,443 B2
• Time in Patent Office: Days
• US Class Current: 714/746
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06

Abstract

A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling.Compliance state for the failure on the PCI Express interconnect, and if the failure override bit has been set, entering PCI Express Polling.Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.

Claims

1. A method, comprising:

discovering a failure on a PCI Express interconnect;

determining whether a failure override bit has been set to override the standard PCI Express Polling.Compliance state for the failure on the PCI Express interconnect; and

if the failure override bit has been set, entering PCI Express Polling.Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.

2. The method of claim 1, wherein discovering a failure on a PCI Express interconnect further comprises:

detecting a receiver in all lanes of a multi-lane PCI Express interconnect during PCI Express Detect.Active state; and

detecting exit from electrical idle in at least one but not all lanes of a multi-lane PCI Express interconnect in PCI Express Polling.Active state.

3. The method of claim 2, further comprising operating the PCI Express multi-lane interconnect in a degraded mode without use of the one or more lanes that did not detect exit from electrical idle.

4. The method of claim 1, wherein discovering a failure on a PCI Express interconnect further comprises detecting a receiver in at least one but not all lanes of a multi-lane PCI Express interconnect during PCI Express Detect.Active state.

5. The method of claim 4, further comprising:

sending training sequence requirements in all lanes that detected a receiver during PCI Express Polling.Active state; and

sending a pattern in the one or more lanes that did not detect a receiver during PCI Express Polling.Active state.

6. The method of claim 5, further comprising operating the PCI Express multi-lane interconnect in a degraded mode without use of the one or more lanes that did not detect a receiver.

7. The method of claim 1, wherein the failure override bit further comprises a bit in a hardware configuration register.

8. The method of claim 1, further comprising:

exiting from the PCI Express Polling.Compliance state if currently in the PCI Express Polling.Compliance state when the failure override bit is set at any time; and

not entering Polling.Compliance state if at least one of the lanes is operational.

9. The method of claim 4, further comprising sending training sequence requirements in all lanes.

10. A device, comprising:

a hardware configuration register;

a failure discovery unit operable to detect failures on a PCI Express interconnect; and

a link training and status state machine operable to;

determine whether a failure override bit in the hardware configuration register has been set to override a failure on the PCI Express interconnect; and

if the failure override bit has been set, enter PCI Express Polling.Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.

11. The device of claim 10, further operable to:

detect a receiver in all lanes of a multi-lane PCI Express interconnect during PCI Express Detect.Active state; and

detect exit from electrical idle at least one lane of a multi-lane PCI Express interconnect in PCI Express Polling.Active state.

12. The device of claim 11, wherein the device is further operable to allow the PCI Express multi-lane interconnect to operate in a degraded mode without use of the one or more lanes that did not detect exit from electrical idle.

13. The device of claim 10, further operable to detect a receiver in at least one but not all lanes of a multi-lane PCI Express interconnect during PCI Express Detect.Active state.

14. The device of claim 13, further operable to:

send training sequence requirements in all lanes that detected a receiver during PCI Express Polling.Active state; and

send a pattern in the one or more lanes that did not detect a receiver during PCI Express Polling.Active state.

15. The device of claim 14, wherein the device is further operable to allow the PCI Express multi-lane interconnect to operate in a degraded mode without use of the one or more lanes that did not detect a receiver.

16. A system, comprising:

a multi-lane PCI Express interconnect;

a first device coupled to the interconnect;

a second device, coupled to the interconnect, comprising;

a hardware configuration register;

a failure discovery unit operable to detect failures on a PCI Express interconnect; and

a link training and status state machine operable to;

determine whether a failure override bit in the hardware configuration register has been set to override a failure on the PCI Express interconnect; and

if the failure override bit has been set, allow the second device to enter PCI Express Polling.Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.

17. The system of claim 16, wherein the failure discovery unit is further operable to:

detect a receiver in all lanes of a multi-lane PCI Express interconnect during PCI Express Detect.Active state; and

detect exit from electrical idle in at least one lane of a multi-lane PCI Express interconnect in PCI Express Polling.Active state.

18. The system of claim 16, wherein the failure discovery unit is further operable to detect a receiver in at least one but not all lanes of a multi-lane PCI Express interconnect during PCI Express Detect.Active state.

19. The system of claim 18, wherein the link training and status state machine is further operable to:

send training sequence requirements in all lanes that detected a receiver during PCI Express Polling.Active state; and

send a pattern in the one or more lanes that did not detect a receiver during PCI Express Polling.Active state.