Mitigating silent data corruption in a buffered memory module architecture

• US 20070011562A1
• Filed: 06/24/2005
• Published: 01/11/2007
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cheng, Kai, Chittor, Suresh, Brzezinski, Dennis, Alexander, James
• Granted Patent: US 7,734,980 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Abstract

Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a first agent to be coupled with a buffered memory module channel, the first agent having an M-bit cyclic redundancy check (CRC) implementation and an N-bit CRC implementation, wherein the N-bit CRC implementation is to be selected if at least one bit-lane of the buffered memory module channel fails;

a second agent coupled with the buffered memory module channel, the second agent to indicate whether data received from the buffered memory module channel contains a correctable error; and

a third agent coupled with the second agent, the third agent capable of signaling a data retry if at least one bit-lane of the buffered memory module channel fails and the second agent indicates a correctable error.

2. The apparatus of claim 1, wherein the apparatus is to operate if there is one of a bit-lane failure or a memory device failure but not both.

3. The apparatus of claim 2, wherein the memory device is a dynamic random access memory (DRAM) device.

4. The apparatus of claim 1, wherein M is twelve and N is six.

5. The apparatus of claim 1, wherein the second agent is, at least in part, an implementation of an error correction code (ECC).

6. The apparatus of claim 5, wherein the implementation of the ECC is an implementation of a single b-bit error correcting-double bit error detecting (SbEC-DED) ECC.

7. The apparatus of claim 6, wherein the correctable error is an ECC-correctable error.

8. The apparatus of claim 7, wherein the buffered memory module channel is a fourteen-bit buffered memory module channel.

9. A method comprising:

receiving, at a first agent, a data packet from a buffered memory module channel, the first agent having an M-bit CRC and an N-bit CRC, wherein the N-bit CRC is to be applied to the data packet if at least one bit-lane of the buffered memory module channel fails;

detecting that at least one bit-lane of the buffered memory module channel has failed;

detecting a correctable error in the data packet based, at least in part, on an error correction code and validating that error through data retransmission and comparison; and

recovering, at least in part, a silent error rate (SER) budget based, at least in part, on a retry operation if the data packet contains a correctable error.

10. The method of claim 9, wherein recovering, at least in part, the silent error rate (SER) budget based, at least in part, on the retry operation if the data packet contains a correctable error comprises:

retrying the data packet to obtain a new data packet;

comparing at least a portion of the data packet to at least a portion of the new data packet; and

processing the data packet with an error correction code, if the data packet substantially matches the new data packet.

11. The method of claim 9, wherein M is twelve and N is six.

12. The method of claim 11, wherein the buffered memory module channel is a fourteen-bit buffered memory module channel.

13. The method of claim 12, wherein the ECC is a sixteen-bit ECC.

14. The method of claim 9, wherein detecting the correctable error in the data packet comprises:

detecting an ECC-correctable error in the data packet.

15. A system comprising:

a memory device coupled with a buffered memory module channel;

a memory channel bit-lane error detector coupled with the buffered memory module channel, the memory channel bit-lane error detector having an M-bit CRC and an N-bit CRC, wherein the N-bit CRC is to be selected if at least one bit-lane of the buffered memory module channel fails;

a memory content error detector coupled with the buffered memory module channel, the memory content error detector to indicate whether data received from the buffered memory module channel contains a correctable error; and

a retry engine coupled with the memory content error detector, the retry engine capable of signaling a data retry if at least one bit-lane of the buffered memory module channel fails and the memory content error detector indicates a correctable error.

16. The system of claim 15, wherein the memory device is a dynamic random access memory device (DRAM) device.

17. The system of claim 16, wherein the DRAM device is a Synchronous DRAM device.

18. The system of claim 15, wherein M is twelve and N is six.

19. The system of claim 18, wherein the buffered memory module channel is a fourteen bit buffered memory module channel.

20. The system of claim 19, wherein the ECC is a sixteen-bit ECC.

21. The system of claim 15, wherein the memory channel bit-lane error detector, the memory content error detector, and the retry engine are integrated into a memory controller.

22. An article of manufacture comprising:

an electronically accessible medium providing instructions that, when executed by an apparatus, cause the apparatus to

receive, at a first agent, a data packet from a buffered memory module channel, the first agent having an M-bit CRC and an N-bit CRC, wherein the N-bit CRC is to be applied to the data packet if at least one bit-lane of the buffered memory module channel fails;

detect that at least one bit-lane of the buffered memory module channel has failed;

detect a correctable error in the data packet based, at least in part, on an error correction code and validating that error through data retransmission and comparison; and

recover, at least in part, a silent error rate (SER) budget based, at least in part, on a retry operation if the data packet contains a correctable error.

23. The article of manufacture of claim 22, wherein the instructions that cause the apparatus to recover, at least in part, the silent error rate (SER) budget based, at least in part, on the retry operation if the data packet contains a correctable error cause the apparatus to:

retry the data packet to obtain a new data packet;

compare at least a portion of the data packet to at least a portion of the new data packet; and

process the data packet with an error correction code, if the data packet substantially matches the new data packet.

24. The article of manufacture of claim 22, wherein M is twelve and N is six.

25. The article of manufacture of claim 22, wherein the buffered memory module channel is a fourteen-bit fully-buffered memory module channel.