Analog bus driver and multiplexer

• US 20070012870A1
• Filed: 06/16/2006
• Published: 01/18/2007
• Est. Priority Date: 06/17/2005
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Pain, Bedabrata, Hancock, Bruce, Cunningham, Thomas
• Granted Patent: US 8,164,663 B2
• Time in Patent Office: Days
• US Class Current: 250/214.R
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/6153 for colour signals
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 3/1568 for disturbance correction or prevention within the image-sensor, e.g. biasing, blooming, smearing correction circuits H04N25/62

Abstract

For a source-follower signal chain, the ohmic drop in the selection switch causes unacceptable voltage offset, non-linearity, and reduced small signal gain. For an op amp signal chain, the required bias current and the output noise rises rapidly with increasing the array format due to a rapid increase in the effective capacitance caused by the Miller effect boosting up the contribution of the bus capacitance. A new switched source-follower signal chain circuit overcomes limitations of existing op-amp based or source follower based circuits used in column multiplexers and data readout. This will improve performance of CMOS imagers, and focal plane read-out integrated circuits for detectors of infrared or ultraviolet light.

Claims

1. An analog bus driver and multiplexer circuit for a detector comprising an array of pixels, the pixels being read out by columns, the circuit comprising a switched source-follower in each column connected by a bus common to the columns.

2. The analog bus driver and multiplexer circuit according to claim 1 wherein the switched source-follower is connected to an operational amplifier.

3. The analog bus driver and multiplexer circuit according to claim 1 wherein the array of pixels is on a focal plane.

4. The analog bus driver and multiplexer circuit according to claim 1 wherein the detector detects one of the group consisting of visible light, infrared light, and ultraviolet light.

5. The analog bus driver and multiplexer circuit according to claim 1 wherein the switched source-follower in each column comprises a load Field Effect Transistor (FET), a switch FET between the source follower FET and the load FET, and a source-follower FET.

6. The analog bus driver and multiplexer circuit according to claim 1 wherein the switched source-follower in each column comprises a switch Field Effect Transistor (FET) connected to a source follower FET, and further comprising a load FET connected to a bias bus.

7. The analog bus driver and multiplexer circuit according to claim 5 wherein the load, source-follower, and switch FETs are of the same type, being either p- or n-channel FETs.

8. The analog bus driver and multiplexer circuit according to claim 6 wherein the load, source-follower, and switch FETs are of the same type, being either p- or n-channel FETs.

9. The analog horizontal bus driver and multiplexer circuit according to claim 5 further comprising a sample-and-hold capacitor, the sample and hold capacitor being connected to the gate of the source-follower FET.

10. The analog horizontal bus driver and multiplexer circuit according to claim 6 further comprising a sample-and-hold capacitor, the sample and hold capacitor being connected to the gate of the source-follower FET.

11. The analog bus driver and multiplexer circuit according to claim 5 further comprising a select FET, the select FET being connected to the output of the source-follower and to the bus.

12. The analog bus driver and multiplexer circuit according to claim 6 further comprising a select FET, the select FET being connected to the output of the source-follower and to the bus.

13. The analog bus driver and multiplexer circuit according to claim 5 further comprising a power bus, wherein the load FET is connected to the power bus if the load FET is a p-channel FET.

14. The analog bus driver and multiplexer circuit according to claim 5 further comprising a ground bus, wherein the load FET is connected to the ground bus if the load FET is an n-channel FET.

15. The analog bus driver and multiplexer circuit according to claim 5 whereby the switched source follower is activated by turning on the switch FET, and establishing steady current flow in the switch FET, the source-follower FET and the load FET.

16. The analog bus driver and multiplexer circuit according to claim 6 whereby the switched source follower is activated by turning on the switch FET, and establishing steady current flow in the switch FET, the source-follower FET and the load FET.

17. The analog bus driver and multiplexer circuit according to claim 11 in which the select FET is a composite FET.

18. The analog bus driver and multiplexer circuit according to claim 12 in which the select FET is a composite FET.

19. A detector of radiation, comprising:

an array of pixels, wherein the pixels are read out by columns; and

at least one analog bus driver and multiplexer circuit for readout, the circuit comprising;

a switched source-follower in each column connected to a bus common to the columns.

20. The detector according to claim 19, wherein the switched source-follower is connected to an operational amplifier.

21. The detector according to claim 19 in which the array of pixels comprises a two-dimensional (2-D) pixel array, and the detector further comprises a one-dimensional array of column sample and hold circuits, row decoder and logic circuit arrays, and column decoder and logic circuit arrays to access the pixels in the array of pixels for reading.

22. The detector according to claim 19 wherein the pixels, columns, and at least one analog bus driver and multiplexer circuits for readout are embodied in an integrated circuit on a substrate.

23. The detector according to claim 22 wherein the integrated circuit is a complementary metal oxide semiconductor circuit.

24. The detector according to claim 19 wherein the at least one analog bus driver and multiplexer circut for readout is embodied in an integrated circuit and the pixels are embodied in a separate focal-plane array connected to the integrated circuit.

25. The detector according to claim 19 in which the pixels comprise means for accumulating charge in response to exposure to one of visible light, infrared light, and ultraviolet light.

26. A method for readout of a detector comprising a focal plane array of pixels, wherein the pixels are read out by columns, comprising:

providing a switched source-follower in each column followed by a switched-capacitor gain stage common to the columns;

sequentially reading out each column by switching the source-follower in each column to connect the source-follower output to a bus common to the columns;

passing the source-follower output through the bus to the switched-capacitor gain stage.

27. The method of claim 26 wherein the switched-capacitor stage comprises an operational amplifier.

28. An analog bus driver and multiplexer circuit for an imager, the circuit comprising:

a plurality of columns, each column comprising a switched source-follower; and

a switched capacitor gain stage common to the plurality of columns, each source follower being connected to the switched capacitor gain stage.

29. The circuit of claim 28, wherein the switched source-follower comprises:

a load field emitter transistor (FET) connected to a power bus;

an out FET; and

a source-follower FET connected to a sample-and-hold capacitor.

30. The circuit of claim 29 further comprising a select FET and a bus connected to the switched capacitor gain stage, the select FET being connected to the output of the source-follower FET and to the bus.