Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
First Claim
1. A semiconductor device comprising:
- a semiconductor substrate; and
at least one metal oxide semiconductor field-effect transistor (MOSFET) thereon comprising spaced-apart source and drain regions, a channel between the source and drain regions, said channel comprising a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor monolayers, and a gate overlying said channel and defining an interface therewith, said gate comprising a gate dielectric overlying said channel and a gate electrode overlying said gate dielectric;
said at least one non-semiconductor monolayer being positioned at depth of about 4-100 monolayers relative to the interface between said channel and said gate dielectric.
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Accused Products
Abstract
A semiconductor device may include a semiconductor substrate, and at least one metal oxide semiconductor field-effect transistor (MOSFET) thereon. The MOSFET may include spaced-apart source and drain regions, a channel between the source and drain regions, and a gate overlying the channel defining an interface therewith. The gate may include a gate dielectric overlying the channel and a gate electrode overlying the gate dielectric. The channel may include a plurality of stacked base semiconductor monolayers, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor monolayers. The at least one non-semiconductor monolayer may be positioned at depth of about 4-100 monolayers relative to the interface between the channel and the gate dielectric.
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Citations
12 Claims
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1. A semiconductor device comprising:
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a semiconductor substrate; and
at least one metal oxide semiconductor field-effect transistor (MOSFET) thereon comprising spaced-apart source and drain regions, a channel between the source and drain regions, said channel comprising a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor monolayers, and a gate overlying said channel and defining an interface therewith, said gate comprising a gate dielectric overlying said channel and a gate electrode overlying said gate dielectric;
said at least one non-semiconductor monolayer being positioned at depth of about 4-100 monolayers relative to the interface between said channel and said gate dielectric. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor device comprising:
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a semiconductor substrate; and
at least one metal oxide semiconductor field-effect transistor (MOSFET) thereon comprising spaced-apart source and drain regions, a channel between the source and drain regions, said channel comprising a plurality of stacked base silicon monolayers and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon monolayers, and a gate overlying said channel and defining an interface therewith, said gate comprising a gate dielectric overlying said channel and a gate electrode overlying said gate dielectric;
said at least one oxygen monolayer being positioned at depth of about 4-100 monolayers relative to the interface between said channel and said gate dielectric. - View Dependent Claims (10, 11, 12)
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Specification
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- Resources
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Current AssigneeMears Technologies Incorporated
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Original AssigneeRJ Mears LLC (Atomera Incorporated)
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InventorsHytha, Marek, Kreps, Scott, Mears, Robert
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Application NumberUS11/457,299Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current257/15CPC Class CodesH01L 29/1054 with a variation of the com...H01L 29/152 with quantum effects only i...H01L 29/78 with field effect produced ...
