Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors

• US 20070012946A1
• Filed: 08/18/2006
• Published: 01/18/2007
• Est. Priority Date: 12/01/2004
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Igor Sankin, Jeffrey Casady, Joseph Merrett
• Inventors: Sankin, Igor, Merrett, Joseph, Casady, Jeffrey
• Granted Patent: US 7,242,040 B2
• Time in Patent Office: Days
• US Class Current: 257/134
• CPC Class Codes: H01L 27/098 the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/8122 Vertical transistors SIT, PBT H01L29/7722

Abstract

A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.

Claims

1-9. -9. (canceled)

10. A semiconductor device comprising:

a substrate having opposed first and second major surfaces; and

a first and a second junction field-effect transistor each on a discrete location on the first major surface of the substrate, each of the junction field-effect transistors comprising;

a drain layer of an n-type semiconductor material on and non-coextensive with the first surface of the substrate such that portions of the substrate surrounding the drain layer are exposed;

a drift layer of an n-type semiconductor material on and non-coextensive with the drain layer such that portions of the drain layer are exposed, the drift layer having a lower conductivity than the drain layer;

one or more discrete raised regions in spaced relation on the drift layer, each of the raised regions comprising a channel region of an n-type semiconductor material on the drift layer and a source region of an n-type semiconductor material on the channel region, the material of the source region having a higher conductivity than that of the channel region;

a gate region of a p-type semiconductor material on the drift layer adjacent the one or more raised regions and forming a rectifying junction with n-type material of the drift layer and the channel region(s); and

ohmic contacts on the gate and source regions and on exposed portions of the drain layer.

11. The semiconductor device of claim 10, wherein the first junction field-effect transistor has a first threshold voltage and the second junction field-effect transistor has a second threshold voltage different than the first threshold voltage.

12. A method of making a junction field-effect transistor comprising:

selectively etching a multi-layered structure comprising;

a substrate having opposed first and second major surfaces;

a drain layer of an n-type semiconductor material on the first major surface of the substrate;

a drift layer of an n-type semiconductor material on the drain layer, the drift layer having a lower conductivity than the drain layer;

a channel layer of an n-type semiconductor material on the drift layer between and in contact with adjacent gate regions; and

a source layer of an n-type semiconductor material on the channel region, the source layer having a higher conductivity than the channel layer;

wherein selectively etching comprises selectively etching through the source layer and partially through the channel layer to form at least one raised source region;

selectively implanting ions of a p-type dopant in exposed portions of the channel layer adjacent the raised source region;

selectively etching through exposed portions of the implanted channel layer and underlying drift layer to expose underlying drain layer; and

selectively etching through exposed portions of the drain layer to expose underlying substrate thereby forming an etched structure.

13. The method of claim 12, further comprising annealing after selectively implanting ions of a p-type dopant to activate the dopant.

14. The method of claim 12, further comprising:

growing or depositing a layer of dielectric material on exposed surfaces of the etched structure;

anisotropically etching the dielectric material to expose underlying portions of drain, gate and source regions parallel to the first surface of the substrate; and

depositing metal on exposed portions of drain, gate and source regions.

15. The method of claim 14, wherein the semiconductor material is SiC, the method further comprising:

annealing after depositing metal on exposed portions of drain, gate and source regions such that metal at metal/semiconductor material interfaces reacts to form metal silicide; and

removing unreacted metal.

16. The method of claim 15, wherein unreacted metal is removed using an acid etch.

17. The method of claim 12, wherein a plurality of raised source regions are formed.

18. The method of claim 17, wherein the plurality of raised source regions are elongate and have a major and a minor dimension and wherein the major dimensions of the raised source regions are oriented parallel to one another.

19. The method of claim 18, wherein the plurality of raised source regions are spaced apart from one another at regular intervals in the direction of the minor dimension.

20. The method of claim 12, wherein multiple etched structures are formed on a single substrate and wherein etching through the drain layer isolates each etched structure.

21. A method of making a field-effect transistor comprising:

selectively implanting a p-type dopant on a multi-layered structure comprising;

a substrate having opposed first and second surfaces;

a drain layer of an n-type semiconductor material on the first surface of the substrate;

a drift layer of an n-type semiconductor material on the drain layer, the drift layer having a lower conductivity than the drain layer; and

wherein selectively implanting comprises selectively implanting the p-type dopant in the drift layer to form a gate region;

depositing or growing a channel layer of an n-type semiconductor material on the implanted surface of the drift layer; and

depositing or growing a source layer of an n-type semiconductor material on the channel layer, the source layer having a higher conductivity than the channel layer;

selectively etching through the source layer, the channel layer and the implanted drift layer to expose underlying drain layer thereby forming raised source/gate regions; and

selectively etching through portions of the exposed drain layer to expose underlying substrate thereby forming an etched structure.

22. A method of making a field-effect transistor comprising:

selectively etching a multi-layered structure comprising;

a substrate having opposed first and second surfaces;

a drain layer of an n-type semiconductor material on the first surface of the substrate;

a drift layer of an n-type semiconductor material on the drain layer, the drift layer having a lower conductivity than the drain layer;

a channel layer of an n-type semiconductor material on the drift layer; and

a source layer of an n-type semiconductor material on the channel region, the source layer having a higher conductivity than the channel layer;

wherein selectively etching comprises selectively etching through the source and channel layers to expose underlying drift layer thereby forming at least one raised source region;

selectively etching through exposed portions of the drift layer to expose underlying drain layer;

selectively etching through exposed portions of the drain layer to expose underlying substrate thereby forming an etched structure; and

selectively depositing a Schottky metal in contact with exposed portions of the drift layer.

23. A field-effect transistor comprising:

a substrate having opposed first and second major surfaces;

a drain layer of an n-type semiconductor material on the first major surface of the substrate;

a drift layer of an n-type semiconductor material on the drain layer and non-coextensive therewith such that portions of the drain layer are exposed, the drift layer having a lower conductivity than the drain layer;

one or more discrete raised regions in spaced relation on the drift layer, each of the raised regions comprising a channel region of an n-type semiconductor material on the drift layer and a source region of an n-type semiconductor material on the channel region, the n-type semiconductor material of the source region having a higher conductivity than that of the channel region;

a metal layer on the drift layer adjacent the one or more raised regions forming a metal-semiconductor rectifying junction with the drift layer and channel region(s); and

ohmic contacts on the source region and on exposed surfaces of the drain layer.

24. The field-effect transistor of claim 23, wherein the source region is coextensive with the channel region.

25-27. -27. (canceled)