Terminations for semiconductor devices with floating vertical series capacitive structures

• US 20070012983A1
• Filed: 07/14/2006
• Published: 01/18/2007
• Est. Priority Date: 07/15/2005
• Status: Abandoned Application

• Current Assignee: Fultec Semiconductor, Inc. (Bourns Incorporated)
• Original Assignee: Fultec Semiconductor, Inc. (Bourns Incorporated)
• Inventors: Hebert, Francois, Blanchard, Richard, Yang, Robert
• Application Number:
  US11/487,142
• Publication Number:
  US 20070012983A1
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention relates to achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage V_BD is maximized and on-resistance is minimized. A second series capacitive structure disposed in a second insulating trench can be employed to terminate the device.

Claims

1. A semiconductor device comprising:

a) a top region, an intermediate region, and a bottom region;

b) a controllable current path traversing any of said regions;

c) a first insulating trench coextensive with and girding said top region and said intermediate region;

d) a first series capacitive structure disposed in said insulating trench and having a biased top element;

wherein said intermediate region has a capacitive property for establishing a capacitive coupling between said first series capacitive structure and said intermediate region, thereby obtaining a high breakdown voltage in said current path; and

e) a termination structure electrically coupled to said first series capacitive structure for controlling an electric field distribution at a periphery of said semiconductor device, thereby obtaining an acceptable breakdown voltage in said termination structure.

2. The device of claim 1, wherein said termination structure comprises a capacitive field plate termination structure having one or more capacitive field plates disposed at a top part of said termination structure.

3. The device of claim 2, wherein a doping density of said termination region is substantially lower than a doping density of said intermediate region.

4. The device of claim 2, wherein said one or more field plates are disposed to enclose said top region of said semiconductor device.

5. The device of claim 2, wherein said capacitive field plates comprise a material selected from the group consisting of:

metals, polysilicon, silicides, conductors, and multi-layer combinations thereof.

6. The device of claim 1, wherein said termination structure comprises a resistive field plate termination structure including:

a termination semiconductor region around said insulating trench

a termination insulating region around said termination semiconductor region

a resistive field plate around said termination insulating region, wherein said resistive field plate is electrically connected to said bottom region; and

a PN junction disposed at a top part of said termination semiconductor region, between said insulating trench and said termination insulating region.

7. The device of claim 6, wherein said resistive field plate comprises semi-insulating polysilicon.

8. The device of claim 6, wherein said termination insulating region comprises oxide.

9. The device of claim 6, wherein a thickness of said termination semiconductor region is selected to enhance uniformity of said electric field distribution.

10. The device of claim 1, wherein said termination structure comprises a vertical trench series capacitive termination structure including:

a termination semiconductor region around said first insulating trench;

a second insulating trench around said termination semiconductor region;

a second series capacitive structure disposed in said second insulating trench.

11. The device of claim 10, wherein said termination semiconductor region comprises a conducting channel.

12. The device of claim 10, wherein a passivation layer is disposed on an outward facing surface of said second insulating trench.

13. The device of claim 12, wherein said passivation layer comprises a material selected from the group consisting of oxides, nitrides, doped silicon dioxide, undoped silicon dioxide, silicon nitride, plasma-deposited nitride, silicon carbide, and diamond-like films.

14. The device of claim 10, wherein a thickness of said termination semiconductor region is selected such that a breakdown location within said termination semiconductor region is away from said first insulating trench and is away from said second insulating trench.

15. The device of claim 10, wherein a thickness of said termination semiconductor region is selected such that a breakdown location within said termination semiconductor region is near a top surface of said termination semiconductor region.

16. A method for maximizing the breakdown voltage in a semiconductor device having a top region, an intermediate region and a bottom region and a controllable current path traversing any of said regions, said method comprising:

a) providing a first insulating trench coextensive with and girding said top region and said intermediate region;

b) disposing a first series capacitive structure in said insulating trench;

c) biasing a top element of said series capacitive structure;

d) adjusting a capacitive property of said intermediate region to establish a capacitive coupling between said series capacitive structure and said intermediate region to obtain a high breakdown voltage in said current path; and

e) controlling an electric field distribution at a periphery of said semiconductor device with a termination structure electrically coupled to said first series capacitive structure, thereby obtaining an acceptable breakdown voltage in said termination structure.

17. The method of claim 16, wherein said termination structure comprises a capacitive field plate termination structure having one or more capacitive field plates disposed on top of a termination region.

18. The method of claim 16, wherein said termination structure comprises a resistive field plate termination structure including:

a termination semiconductor region around said insulating trench

a termination insulating region around said termination semiconductor region

a resistive field plate around said termination insulating region, wherein said resistive field plate is electrically connected to said bottom region; and

a PN junction disposed at a top part of said termination semiconductor region, between said insulating trench and said termination insulating region.

19. The method of claim 16, wherein said termination structure comprises a vertical trench series capacitive termination structure including:

a termination semiconductor region around said first insulating trench;

a second insulating trench around said termination semiconductor region;

a second series capacitive structure disposed in said second insulating trench.

20. A semiconductor device having cells, each of said cells comprising:

a) a top region, an intermediate region and a bottom region;

b) a controllable current path traversing any of said regions;

c) an insulating trench coextensive with and girding said top region and said intermediate region;

d) a series capacitive structure disposed in said insulating trench and having a biased tip conductor;

said intermediate region having a capacitive property establishing a capacitive coupling between said series capacitive structure and said intermediate region, thereby obtaining a high breakdown voltage in said current path; and

e) a termination structure electrically coupled to said series capacitive structure for controlling an electric field distribution at a periphery of said semiconductor device, thereby obtaining an acceptable breakdown voltage in said termination structure.