N-ary Mask-Programmable Memory

• US 20070013003A1
• Filed: 09/02/2005
• Published: 01/18/2007
• Est. Priority Date: 07/15/2005
• Status: Active Grant

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Granted Patent: US 7,633,128 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H10B 20/38 Doping programmed, e.g. mask ROM
• CPC Class Codes: H10B 20/65 of memory structures of the ROM only type

Abstract

The present invention discloses an N-ary mask-programmable memory (N-MPM). N-MPM cells can have N cell-states, with N>2. N-MPM cells could be geometry-defined, junction-defined, or both. Based on an nF-opening process (n≧1), partial-contacts with feature size<1F can be implemented with an nF-opening mask with feature size≧1F. N can be a non-integral power of 2. In this case, each memory cell represents fractional bits.

Claims

1. An N-ary mask-programmable memory, comprising:

a plurality of lower address-selection lines;

a plurality of upper address-selection lines above said lower address-selection lines; and

a plurality of mask-programmable memory cells located at the intersections of said lower and upper address-selection lines, said memory cells having N distinct cell-states with N>

2.

2. The N-ary mask-programmable memory according to claim 1, wherein each of said cell-states conducts a distinct read current at a same read voltage.

3. The N-ary mask-programmable memory according to claim 1, wherein each of said cell-states has a distinct geometry.

4. The N-ary mask-programmable memory according to claim 1, further comprising:

a first memory cell having a first contact-area;

a second memory cell having a second contact-area, said second contact-area being larger in size than said first contact-area; and

a third memory cell having a third contact-area, said third contact-area being larger in size than said second contact-area.

5. The N-ary mask-programmable memory according to claim 4, further comprising an upper and lower address-selection lines, wherein said upper address-selection line makes electrical contact with said lower address-selection line at said first contact-area, and said first contact-area is located at an edge of said upper address-selection line.

6. The N-ary mask-programmable memory according to claim 4, further comprising a first and second upper address-selection lines, wherein:

said first upper address-selection line is parallel and adjacent to said second upper address-selection line;

said first contact-area is located at a first edge of said first upper address-selection line;

said second contact-area is located at a second edge of said second upper address-selection line; and

said first edge faces towards said second upper address-selection line and said second edge faces towards said first upper address-selection line.

7. The N-ary mask-programmable memory according to claim 1, further comprising:

an insulating dielectric between said lower and upper address-selection lines; and

an opening in said insulating dielectric, selected one(s) of said upper address-selection lines making electrical contact(s) with selected one(s) of said lower address-selection lines through said opening;

wherein said opening intersects at least two lower address-selection lines or at least two upper address-selection lines.

8. The N-ary mask-programmable memory according to claim 4, wherein the size difference between said second and first contact-areas is not equal to the size difference between said third and second contact-areas.

9. The N-ary mask-programmable memory according to claim 4, further comprising a dummy cell having a dummy contact-area, wherein the size of said dummy contact-area is between said first and second contact-areas.

10. The N-ary mask-programmable memory according to claim 1, wherein each of said cell-states has a distinct junction.

11. The N-ary mask-programmable memory according to claim 1, further comprising a first and second memory cells, wherein said first and second memory cells have different doping profiles.

12. The N-ary mask-programmable memory according to claim 11, further comprising a current-limiting circuit in connection with said first cell for limiting the current flow in said cell.

13. The N-ary mask-programmable memory according to claim 1, wherein at least two read voltages are applied in sequence to selected ones of said memory cells during read.

14. The N-ary mask-programmable memory according to claim 1, further comprising a plurality of dummy cells and a plurality of comparators, wherein the output from a selected one of said memory cells is compared with the output from a selected one of said dummy cells at a selected one of said comparators.

15. The N-ary mask programmable memory according to claim 14, further comprising:

a first and second dummy cells; and

a first and second comparators, each comparator comprising a first and second inputs;

wherein, said first inputs of said first and second comparators are from a selected one of said memory cells;

said second input of said first comparator is from said first dummy cell;

said second input of said second comparator is from said second dummy cell.

16. The N-ary mask programmable memory according to claim 14, further comprising:

a first and second dummy cells; and

a first and second comparators, each comparator comprising a first and second inputs;

wherein, said first input of said first comparator is from a first selected one of said memory cells;

said first input of said second comparator is from a second selected one of said memory cells;

said second inputs of said first and second comparators are from a selected one of said first and second dummy cells.

17. The N-ary mask-programmable memory according to claim 1, further comprising:

a first and second memory cells;

a first dummy cell in contact with a first dummy address-selection line and having the same structure as said first memory cell; and

a second dummy cell in contact with a second dummy address-selection line and having the same structure as said second memory cell;

wherein said first and second dummy address-selection lines can be connected together.

18. The N-ary mask-programmable memory according to claim 1, further comprising:

a first memory level; and

a second memory level stacked above said first memory level;

wherein at least one of said first and second memory levels comprises said N-ary mask-programmable memory cells.

19. The N-ary mask-programmable memory according to claim 1, wherein N is an integral power of 2.

20. The N-ary mask-programmable memory according to claim 1, wherein N is a non-integral power of 2.