TEST STRUCTURE DESIGN FOR RELIABILITY TEST
First Claim
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1. A method for evaluating parameters of a semiconductor design, comprising:
- generating a semiconductor test structure with at least one conductive line formed in a first metal layer coupled with a plurality of thermal stress-inducing conductive test pads in a second metal layer by a plurality of conductive vias;
taking and recording one or more baseline resistance measurements across at least one of the vias or at least one section of the at least one conductive line;
exposing the test structure to one or more elevated temperatures to generate thermal stress on the test structure;
taking and recording one or more stressed resistance measurements across at least one of the vias or at least one section of the at least one conductive line after exposing the test structure to the one or more elevated temperatures; and
comparing the stressed resistance measurements to the baseline resistance measurements in order to detect voids formed in at least one of the conductive line or the vias.
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Abstract
A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.
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Citations
7 Claims
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1. A method for evaluating parameters of a semiconductor design, comprising:
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generating a semiconductor test structure with at least one conductive line formed in a first metal layer coupled with a plurality of thermal stress-inducing conductive test pads in a second metal layer by a plurality of conductive vias;
taking and recording one or more baseline resistance measurements across at least one of the vias or at least one section of the at least one conductive line;
exposing the test structure to one or more elevated temperatures to generate thermal stress on the test structure;
taking and recording one or more stressed resistance measurements across at least one of the vias or at least one section of the at least one conductive line after exposing the test structure to the one or more elevated temperatures; and
comparing the stressed resistance measurements to the baseline resistance measurements in order to detect voids formed in at least one of the conductive line or the vias. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification