WAFER-LEVEL BURN-IN AND TEST
1 Assignment
0 Petitions
Accused Products
Abstract
Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.
96 Citations
57 Claims
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1-32. -32. (canceled)
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33. :
- Method of performing burn-in on semiconductor devices, comprising;
connecting a test substrate to at least one semiconductor device (DUT);
powering up the at least one DUT;
maintaining the at least one DUT at a first temperature; and
maintaining the test substrate at a second temperature which is independent of the first temperature. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40)
- Method of performing burn-in on semiconductor devices, comprising;
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41-48. -48. (canceled)
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49. :
- Method of aligning a plurality of electronic components to an interconnection substrate, comprising;
forming indentations on a back surface of each electronic component;
forming corresponding indentations on a front surface of the interconnection substrate; and
disposing spherical elements between the indentations and the corresponding indentations. - View Dependent Claims (50)
- Method of aligning a plurality of electronic components to an interconnection substrate, comprising;
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51. :
- Method of effecting connections between tips of elongate interconnection elements extending from a first electronic component and a second electronic component, comprising;
forming indentations on a front surface of the second electronic component;
bringing the first and second electronic components together so that the tips of the elongate interconnection elements are disposed within the indentations; and
moving the second electronic component in a direction selected from the group consisting of laterally or rotationally to effect a pressure connection between tips of the elongate interconnection elements and sidewalls of the indentations. - View Dependent Claims (52, 53, 54, 55, 56)
- Method of effecting connections between tips of elongate interconnection elements extending from a first electronic component and a second electronic component, comprising;
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57-60. -60. (canceled)
Specification